Method for patterning a coating on a surface and device including a patterned coating

ABSTRACT

An opto-electronic device includes: a first electrode; an organic layer disposed over the first electrode; a nucleation promoting coating disposed over the organic layer; a nucleation inhibiting coating covering a first region of the opto-electronic device; and a conductive coating covering a second region of the opto-electronic device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 16/279,930 filed Feb. 19, 2019, which application is a continuation of U.S. patent application Ser. No. 15/527,702, filed May 17, 2017, which is a National Stage Entry of International Application No. PCT/IB2016/056442, filed Oct. 26, 2016, which claims the benefit of and priority to U.S. Provisional Application No. 62/246,597, filed Oct. 26, 2015, U.S. Provisional Application No. 62/277,989, filed Jan. 13, 2016, U.S. Provisional Application No. 62/373,927, filed Aug. 11, 2016, and U.S. Provisional Application No. 62/377,429, filed Aug. 19, 2016, the contents of all such applications being incorporated herein by reference in their entireties.

TECHNICAL FIELD

The following generally relates to a method for depositing an electrically conductive material on a surface. Specifically, the method relates to selective deposition of the electrically conductive material on a surface for forming an electrically conductive structure of a device.

BACKGROUND

Organic light emitting diodes (OLEDs) typically include several layers of organic materials interposed between conductive thin film electrodes, with at least one of the organic layers being an electroluminescent layer. When a voltage is applied to electrodes, holes and electrons are injected from an anode and a cathode, respectively. The holes and electrons injected by the electrodes migrate through the organic layers to reach the electroluminescent layer. When a hole and an electron are in close proximity, they are attracted to each other due to a Coulomb force. The hole and electron may then combine to form a bound state referred to as an exciton. An exciton may decay through a radiative recombination process, in which a photon is released. Alternatively, an exciton may decay through a non-radiative recombination process, in which no photon is released. It is noted that, as used herein, internal quantum efficiency (IQE) will be understood to be a proportion of all electron-hole pairs generated in a device which decay through a radiative recombination process.

A radiative recombination process can occur as a fluorescence or phosphorescence process, depending on a spin state of an electron-hole pair (namely, an exciton). Specifically, the exciton formed by the electron-hole pair may be characterized as having a singlet or triplet spin state. Generally, radiative decay of a singlet exciton results in fluorescence, whereas radiative decay of a triplet exciton results in phosphorescence.

More recently, other light emission mechanisms for OLEDs have been proposed and investigated, including thermally activated delayed fluorescence (TADF). Briefly, TADF emission occurs through a conversion of triplet excitons into singlet excitons via a reverse inter system crossing process with the aid of thermal energy, followed by radiative decay of the singlet excitons.

An external quantum efficiency (EQE) of an OLED device may refer to a ratio of charge carriers provided to the OLED device relative to a number of photons emitted by the device. For example, an EQE of 100% indicates that one photon is emitted for each electron that is injected into the device. As will be appreciated, an EQE of a device is generally substantially lower than an IQE of the device. The difference between the EQE and the IQE can generally be attributed to a number of factors such as absorption and reflection of light caused by various components of the device.

An OLED device can typically be classified as being either a “bottom-emission” or “top-emission” device, depending on a relative direction in which light is emitted from the device. In a bottom-emission device, light generated as a result of a radiative recombination process is emitted in a direction towards a base substrate of the device, whereas, in a top-emission device, light is emitted in a direction away from the base substrate. Accordingly, an electrode that is proximal to the base substrate is generally made to be light transmissive (e.g., substantially transparent or semi-transparent) in a bottom-emission device, whereas, in a top-emission device, an electrode that is distal to the base substrate is generally made to be light transmissive in order to reduce attenuation of light. Depending on the specific device structure, either an anode or a cathode may act as a transmissive electrode in top-emission and bottom-emission devices.

An OLED device also may be a double-sided emission device, which is configured to emit light in both directions relative to a base substrate. For example, a double-sided emission device may include a transmissive anode and a transmissive cathode, such that light from each pixel is emitted in both directions. In another example, a double-sided emission display device may include a first set of pixels configured to emit light in one direction, and a second set of pixels configured to emit light in the other direction, such that a single electrode from each pixel is transmissive.

In addition to the above device configurations, a transparent or semi-transparent OLED device also can be implemented, in which the device includes a transparent portion which allows external light to be transmitted through the device. For example, in a transparent OLED display device, a transparent portion may be provided in a non-emissive region between each neighboring pixels. In another example, a transparent OLED lighting panel may be formed by providing a plurality of transparent regions between emissive regions of the panel. Transparent or semi-transparent OLED devices may be bottom-emission, top-emission, or double-sided emission devices.

While either a cathode or an anode can be selected as a transmissive electrode, a typical top-emission device includes a light transmissive cathode. Materials which are typically used to form the transmissive cathode include transparent conducting oxides (TCOs), such as indium tin oxide (ITO) and zinc oxide (ZnO), as well as thin films, such as those formed by depositing a thin layer of silver (Ag), aluminum (Al), or various metallic alloys such as magnesium silver (Mg:Ag) alloy and ytterbium silver (Yb:Ag) alloy with compositions ranging from about 1:9 to about 9:1 by volume. A multi-layered cathode including two or more layers of TCOs and/or thin metal films also can be used.

Particularly in the case of thin films, a relatively thin layer thickness of up to about a few tens of nanometers contributes to enhanced transparency and favorable optical properties (e.g., reduced microcavity effects) for use in OLEDs. However, a reduction in the thickness of a transmissive electrode is accompanied by an increase in its sheet resistance. An electrode with a high sheet resistance is generally undesirable for use in OLEDs, since it creates a large current-resistance (IR) drop when a device is in use, which is detrimental to the performance and efficiency of OLEDs. The IR drop can be compensated to some extent by increasing a power supply level; however, when the power supply level is increased for one pixel, voltages supplied to other components are also increased to maintain proper operation of the device, and thus is unfavorable.

In order to reduce power supply specifications for top-emission OLED devices, solutions have been proposed to form busbar structures or auxiliary electrodes on the devices. For example, such an auxiliary electrode may be formed by depositing a conductive coating in electrical communication with a transmissive electrode of an OLED device. Such an auxiliary electrode may allow current to be carried more effectively to various regions of the device by lowering a sheet resistance and an associated IR drop of the transmissive electrode.

Since an auxiliary electrode is typically provided on top of an OLED stack including an anode, one or more organic layers, and a cathode, patterning of the auxiliary electrode is traditionally achieved using a shadow mask with mask apertures through which a conductive coating is selectively deposited, for example by a physical vapor deposition (PVD) process. However, since masks are typically metal masks, they have a tendency to warp during a high-temperature deposition process, thereby distorting mask apertures and a resulting deposition pattern. Furthermore, a mask is typically degraded through successive depositions, as a conductive coating adheres to the mask and obfuscates features of the mask. Consequently, such a mask should either be cleaned using time-consuming and expensive processes or should be disposed once the mask is deemed to be ineffective at producing the desired pattern, thereby rendering such process highly costly and complex. Accordingly, a shadow mask process may not be commercially feasible for mass production of OLED devices. Moreover, an aspect ratio of features which can be produced using the shadow mask process is typically constrained due to shadowing effects and a mechanical (e.g., tensile) strength of the metal mask, since large metal masks are typically stretched during a shadow mask deposition process.

Another challenge of patterning a conductive coating onto a surface through a shadow mask is that certain, but not all, patterns can be achieved using a single mask. As each portion of the mask is physically supported, not all patterns are possible in a single processing stage. For example, where a pattern specifies an isolated feature, a single mask processing stage typically cannot be used to achieve the desired pattern. In addition, masks which are used to produce repeating structures (e.g., busbar structures or auxiliary electrodes) spread across an entire device surface include a large number of perforations or apertures formed on the masks. However, forming a large number of apertures on a mask can compromise the structural integrity of the mask, thus leading to significant warping or deformation of the mask during processing, which can distort a pattern of deposited structures.

SUMMARY

According to some embodiments, a device (e.g., an opto-electronic device) includes: (1) a first electrode; (2) an organic layer disposed over the first electrode; (3) a nucleation promoting coating disposed over the organic layer; (4) a nucleation inhibiting coating covering a first region of the opto-electronic device; and (5) a conductive coating covering a second region of the opto-electronic device.

According to some embodiments, a device (e.g., an opto-electronic device) includes: (1) a substrate; (2) a nucleation inhibiting coating covering a first region of the substrate; and (3) a conductive coating including a first portion and a second portion. The first portion of the conductive coating covers a second region of the substrate, the second portion of the conductive coating partially overlaps the nucleation inhibiting coating, and the second portion of the conductive coating is spaced from the nucleation inhibiting coating by a gap.

According to some embodiments, a device (e.g., an opto-electronic device) includes: (1) a substrate including a first region and a second region; and (2) a conductive coating including a first portion and a second portion. The first portion of the conductive coating covers the second region of the substrate, the second portion of the conductive coating overlaps a portion of the first region of the substrate, and the second portion of the conductive coating is spaced from the first region of the substrate by a gap.

According to some embodiments, a device (e.g., an opto-electronic device) includes: (1) a substrate; (2) a nucleation inhibiting coating covering a first region of the substrate; and (3) a conductive coating covering a laterally adjacent, second region of the substrate. The conductive coating includes magnesium, and the nucleation inhibiting coating is characterized as having an initial sticking probability for magnesium of no greater than about 0.02.

According to some embodiments, a manufacturing method of a device (e.g., an opto-electronic device) includes: (1) providing a substrate and a nucleation inhibiting coating covering a first region of the substrate; and (2) depositing a conductive coating covering a second region of the substrate. The conductive coating includes magnesium, and the nucleation inhibiting coating is characterized as having an initial sticking probability for magnesium of no greater than 0.02.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments will now be described by way of example with reference to the appended drawings wherein:

FIG. 1 is a schematic diagram illustrating a shadow mask deposition of a nucleation inhibiting coating according to one embodiment;

FIG. 2A, FIG. 2B, and FIG. 2C are schematic diagrams illustrating a micro-contact transfer printing process of a nucleation inhibiting coating according to one embodiment;

FIG. 3 is a schematic diagram illustrating the deposition of a conductive coating on a patterned surface according to one embodiment;

FIG. 4 is a diagram illustrating a device produced according to one embodiment of a process;

FIGS. 5A-5C are schematic diagrams illustrating a process for selectively depositing a conductive coating according to one embodiment;

FIGS. 5D-5F are schematic diagrams illustrating a process for selectively depositing a conductive coating according to another embodiment;

FIG. 6 is a diagram illustrating an electroluminescent device according to one embodiment;

FIG. 7 is a flow diagram showing process stages according to one embodiment;

FIG. 8 is a flow diagram showing process stages according to another embodiment;

FIG. 9A-9D are schematic diagrams illustrating the stages in the embodiment of FIG. 8;

FIG. 10 is a flow diagram showing process stages according to yet another embodiment;

FIGS. 11A-11D are schematic diagrams illustrating the stages in the embodiment of FIG. 10;

FIG. 12 is a flow diagram showing process stages according to yet another embodiment;

FIGS. 13A-13D are schematic diagrams illustrating the stages in the embodiment of FIG. 12;

FIG. 14 is a top view of an OLED device according to one embodiment;

FIG. 15 is a cross-sectional view of the OLED device of FIG. 14;

FIG. 16 is a cross-sectional view of an OLED device according to another embodiment;

FIG. 16B is a top view illustrating an open mask according to one example;

FIG. 16C is a top view illustrating an open mask according to another example;

FIG. 16D is a top view illustrating an open mask according to yet another example;

FIG. 16E is a top view illustrating an open mask according to yet another example;

FIG. 17 is a top view illustrating a patterned electrode according to one embodiment;

FIG. 17B is a schematic diagram illustrating a top view of a passive matrix OLED device according to one embodiment;

FIG. 17C is a schematic cross-sectional view of the passive matrix OLED device of FIG. 17B;

FIG. 17D is a schematic cross-sectional view of the passive matrix OLED device of FIG. 17B after encapsulation;

FIG. 17E is a schematic cross-sectional view of a comparative passive matrix OLED device;

FIGS. 18A-18D illustrate portions of auxiliary electrodes according to various embodiments;

FIG. 19 illustrates a top view of a lead connected to an electrode of an OLED device according to one embodiment;

FIG. 20 illustrates a top view of a patterned electrode according to one embodiment;

FIGS. 21A-21D illustrate patterned electrodes according to various embodiments;

FIG. 22 illustrates repeating electrode units formed on an OLED device according to one embodiment;

FIG. 23 illustrates repeating electrode units formed on an OLED device according to another embodiment;

FIG. 24 illustrates repeating electrode units formed on an OLED device according to yet another embodiment;

FIGS. 25-28J illustrate auxiliary electrode patterns formed on OLED devices according to various embodiments;

FIG. 29 illustrate a portion of a device with a pixel arrangement according to one embodiment;

FIG. 30 is a cross-sectional diagram taken along line A-A of the device according to FIG. 29;

FIG. 31 is a cross-sectional diagram taken along line B-B of the device according to FIG. 29;

FIG. 32 is a diagram illustrating a portion of a device with a pixel arrangement according to another embodiment;

FIG. 33 is a micrograph of a device having the pixel arrangement illustrated in FIG. 32;

FIG. 34 is a diagram illustrating a cross-sectional profile around an interface of a conductive coating and a nucleation inhibiting coating according to one embodiment;

FIG. 35 is a diagram illustrating a cross-sectional profile around an interface of a conductive coating and a nucleation inhibiting coating according to another embodiment;

FIG. 36 is a diagram illustrating a cross-sectional profile around an interface of a conductive coating, a nucleation inhibiting coating, and a nucleation promoting coating according to one embodiment;

FIG. 37 is a diagram illustrating a cross-sectional profile around an interface of a conductive coating, a nucleation inhibiting coating, and a nucleation promoting coating according to another embodiment;

FIG. 38 is a diagram illustrating a cross-sectional profile around an interface of a conductive coating and a nucleation inhibiting coating according to yet another embodiment;

FIG. 39 is a diagram illustrating a cross-sectional profile of an active matrix OLED device according to one embodiment;

FIG. 40 is a diagram illustrating a cross-sectional profile of an active matrix OLED device according to another embodiment;

FIG. 41 is a diagram illustrating a cross-sectional profile of an active matrix OLED device according to yet another embodiment;

FIG. 42 is a diagram illustrating a cross-sectional profile of an active matrix OLED device according to yet another embodiment;

FIG. 43 is a diagram illustrating a transparent active matrix OLED device according to one embodiment;

FIG. 44 is a diagram illustrating a cross-sectional profile of the device according to FIG. 43;

FIG. 45A is a SEM image of a top view of Sample 1;

FIGS. 45B and 45C are SEM images showing a magnified view of a portion of the sample of FIG. 45A;

FIG. 45D is a SEM image showing a cross-sectional view of the sample of FIG. 45A;

FIG. 45E is a SEM image showing a cross-sectional view of the sample of FIG. 45A;

FIG. 45F is a SEM image showing a cross-sectional view of another portion of the sample of FIG. 45A;

FIG. 45G is a tilted SEM image showing the sample portion of FIG. 45F;

FIG. 45H is a plot showing an EDX spectra taken from the sample of FIG. 45A;

FIG. 46A is a SEM image of a top view of Sample 2;

FIG. 46B is a SEM image showing a magnified view of a portion of the sample of FIG. 46A;

FIG. 46C is a SEM image showing a further magnified view of the sample portion of FIG. 46B;

FIG. 46D is a SEM image showing a cross-sectional view of the sample of FIG. 46A;

FIGS. 46E and 46F are tilted SEM images showing a surface of the sample of FIG. 46A;

FIG. 46G is a plot showing an EDX spectra taken from the sample of FIG. 46A;

FIG. 46H shows a magnesium EDX spectrum overlaid on top of an SEM image showing a corresponding portion of the sample from which the spectrum was obtained;

FIG. 47 is a schematic diagram illustrating a chamber set up for conducting deposition experiments using quartz crystal microbalances (QCMs);

FIG. 48 is a circuit diagram showing an example driving circuit for an active matrix OLED display device;

FIG. 49 is a schematic illustration of a magnesium coating deposited between portions of a nucleation inhibiting coating;

FIG. 50A is a SEM image showing a top view of a sample fabricated using a BAlq nucleation inhibiting coating;

FIG. 50B is a SEM image showing a magnified portion of the sample of FIG. 50A;

FIGS. 50C and 50D are SEM images showing magnified portions of the sample of FIG. 50A;

FIG. 50E is a tilted SEM image showing a surface of the sample of FIG. 50A;

FIG. 51A is a SEM image showing a top view of a comparative sample fabricated using a HT211 nucleation inhibiting coating;

FIG. 51B is a cross-sectional SEM image of the comparative sample of FIG. 51A;

FIG. 52A is a SEM image showing a top view of a comparative sample fabricated using shadow mask deposition;

FIG. 52B is a cross-sectional SEM image of the comparative sample of FIG. 52A;

FIG. 53 is a plot of transmittance versus wavelength for comparative samples fabricated with HT211 nucleation inhibiting coatings deposited at various deposition rates;

FIG. 54 is a plot of transmittance versus wavelength for samples fabricated with various nucleation inhibiting coatings;

FIG. 55 is a top view showing a pattern of an auxiliary electrode according to one example embodiment;

FIG. 56 is a plot showing sheet resistance specifications and associated auxiliary electrode thicknesses for various display panel sizes;

FIG. 57 is a plot showing a layer thickness of magnesium deposited on a reference QCM surface versus a layer thickness of magnesium deposited on a sample QCM surface covered with various nucleation modifying coatings;

FIG. 58 is a plot showing a sticking probability of magnesium vapor on a sample QCM surface versus a layer thickness of magnesium deposited on the sample QCM surface covered with various nucleation modifying coatings; and

FIGS. 59A and 59B illustrate a process for removing a nucleation inhibiting coating following deposition of a conductive coating according to one embodiment.

DETAILED DESCRIPTION

It will be appreciated that for simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous components. In addition, numerous specific details are set forth in order to provide a thorough understanding of example embodiments described herein. However, it will be understood by those of ordinary skill in the art that the example embodiments described herein may be practiced without some of those specific details. In other instances, certain methods, procedures and components have not been described in detail so as not to obscure the example embodiments described herein.

In one aspect according to some embodiments, a method for depositing an electrically conductive coating on a surface is provided. In some embodiments, the method is performed in the context of a manufacturing method of an opto-electronic device. In some embodiments, the method is performed in the context of a manufacturing method of another device. In some embodiments, the method includes depositing a nucleation inhibiting coating on a first region of a substrate to produce a patterned substrate. The patterned substrate includes the first region covered by the nucleation inhibiting coating, and a second region of the substrate that is exposed from, or is substantially free of or is substantially uncovered by, the nucleation inhibiting coating. The method also includes treating the patterned substrate to deposit the conductive coating on the second region of the substrate. In some embodiments, a material of the conductive coating includes magnesium. In some embodiments, treating the patterned substrate includes treating both the nucleation inhibiting coating and the second region of the substrate to deposit the conductive coating on the second region of the substrate, while the nucleation inhibiting coating remains exposed from, or is substantially free of or is substantially uncovered by, the conductive coating. In some embodiments, treating the patterned substrate includes performing evaporation or sublimation of a source material used to form the conductive coating, and exposing both the nucleation inhibiting coating and the second region of the substrate to the evaporated source material.

As used herein, the term “nucleation inhibiting” is used to refer to a coating or a layer of a material having a surface which exhibits a relatively low affinity towards deposition of an electrically conductive material, such that the deposition of the conductive material on the surface is inhibited, while the term “nucleation promoting” is used to refer to a coating or a layer of a material having a surface which exhibits a relatively high affinity towards deposition of an electrically conductive material, such that the deposition of the conductive material on the surface is facilitated. One measure of nucleation inhibiting or nucleation promoting property of a surface is an initial sticking probability of the surface for an electrically conductive material, such as magnesium. For example, a nucleation inhibiting coating with respect to magnesium can refer to a coating having a surface which exhibits a relatively low initial sticking probability for magnesium vapor, such that deposition of magnesium on the surface is inhibited, while a nucleation promoting coating with respect to magnesium can refer to a coating having a surface which exhibits a relatively high initial sticking probability for magnesium vapor, such that deposition of magnesium on the surface is facilitated. As used herein, the terms “sticking probability” and “sticking coefficient” may be used interchangeably. Another measure of nucleation inhibiting or nucleation promoting property of a surface is an initial deposition rate of an electrically conductive material, such as magnesium, on the surface relative to an initial deposition rate of the conductive material on another (reference) surface, where both surfaces are subjected or exposed to an evaporation flux of the conductive material.

As used herein, the terms “evaporation” and “sublimation” are interchangeably used to generally refer to deposition processes in which a source material is converted into a vapor (e.g., by heating) to be deposited onto a target surface in, for example, a solid state.

As used herein, a surface (or a certain area of the surface) which is “substantially free of” or “is substantially uncovered by” a material refers to a substantial absence of the material on the surface (or the certain area of the surface). Specifically regarding an electrically conductive coating, one measure of an amount of an electrically conductive material on a surface is a light transmittance, since electrically conductive materials, such as metals including magnesium, attenuate and/or absorb light. Accordingly, a surface can be deemed to be substantially free of an electrically conductive material if the light transmittance is greater than 90%, greater than 92%, greater than 95%, or greater than 98% in the visible portion of the electromagnetic spectrum. Another measure of an amount of a material on a surface is a percentage coverage of the surface by the material, such as where the surface can be deemed to be substantially free of the material if the percentage coverage by the material is no greater than 10%, no greater than 8%, no greater than 5%, no greater than 3%, or no greater than 1%. Surface coverage can be assessed using imaging techniques, such as using transmission electron microscopy, atomic force microscopy, or scanning electron microscopy.

FIG. 1 is a schematic diagram illustrating a process of depositing a nucleation inhibiting coating 140 onto a surface 102 of a substrate 100 according to one embodiment. In the embodiment of FIG. 1, a source 120 including a source material is heated under vacuum to evaporate or sublime the source material. The source material includes or substantially consists of a material used to form the nucleation inhibiting coating 140. The evaporated source material then travels in a direction indicated by arrow 122 towards the substrate 100. A shadow mask 110 having an aperture or slit 112 is disposed in the path of the evaporated source material such that a portion of a flux travelling through the aperture 112 is selectively incident on a region of the surface 102 of the substrate 100, thereby forming the nucleation inhibiting coating 140 thereon.

FIGS. 2A-2C illustrate a micro-contact transfer printing process for depositing a nucleation inhibiting coating on a surface of a substrate in one embodiment. Similarly to a shadow mask process, the micro-contact printing process may be used to selectively deposit the nucleation inhibiting coating on a region of a substrate surface.

FIG. 2A illustrates a first stage of the micro-contact transfer printing process, wherein a stamp 210 including a protrusion 212 is provided with a nucleation inhibiting coating 240 on a surface of the protrusion 212. As will be understood by persons skilled in the art, the nucleation inhibiting coating 240 may be deposited on the surface of the protrusion 212 using various suitable processes.

As illustrated in FIG. 2B, the stamp 210 is then brought into proximity of a substrate 100, such that the nucleation inhibiting coating 240 deposited on the surface of the protrusion 212 is in contact with a surface 102 of the substrate 100. Upon the nucleation inhibiting coating 240 contacting the surface 102, the nucleation inhibiting coating 240 adheres to the surface 102 of the substrate 100.

As such, when the stamp 210 is moved away from the substrate 100 as illustrated in FIG. 2C, the nucleation inhibiting coating 240 is effectively transferred onto the surface 102 of the substrate 100.

Once a nucleation inhibiting coating has been deposited on a region of a surface of a substrate, a conductive coating may be deposited on remaining uncovered region(s) of the surface where the nucleation inhibiting coating is not present. Turning to FIG. 3, a conductive coating source 410 is illustrated as directing an evaporated conductive material towards a surface 102 of a substrate 100. As illustrated in FIG. 3, the conducting coating source 410 may direct the evaporated conductive material such that it is incident on both covered or treated areas (namely, region(s) of the surface 102 with the nucleation inhibiting coating 140 deposited thereon) and uncovered or untreated areas of the surface 102. However, since a surface of the nucleation inhibiting coating 140 exhibits a relatively low initial sticking coefficient compared to that of the uncovered surface 102 of the substrate 100, a conductive coating 440 selectively deposits onto the areas of the surface 102 where the nucleation inhibiting coating 140 is not present. For example, an initial deposition rate of the evaporated conductive material on the uncovered areas of the surface 102 may be at least or greater than about 80 times, at least or greater than about 100 times, at least or greater than about 200 times, at least or greater than about 500 times, at least or greater than about 700 times, at least or greater than about 1000 times, at least or greater than about 1500 times, at least or greater than about 1700 times, or at least or greater than about 2000 times an initial deposition rate of the evaporated conductive material on the surface of the nucleation inhibiting coating 140. The conductive coating 440 may include, for example, pure or substantially pure magnesium.

It will be appreciated that although shadow mask patterning and micro-contact transfer printing processes have been illustrated and described above, other processes may be used for selectively patterning a substrate by depositing a nucleation inhibiting material. Various additive and subtractive processes of patterning a surface may be used to selectively deposit a nucleation inhibiting coating. Examples of such processes include, but are not limited to, photolithography, printing (including ink or vapor jet printing and reel-to-reel printing), organic vapor phase deposition (OVPD), and laser induced thermal imaging (LITI) patterning, and combinations thereof.

In some applications, it may be desirable to deposit a conductive coating having specific material properties onto a substrate surface on which the conductive coating cannot be readily deposited. For example, pure or substantially pure magnesium typically cannot be readily deposited onto an organic surface due to low sticking coefficients of magnesium on various organic surfaces. Accordingly, in some embodiments, the substrate surface is further treated by depositing a nucleation promoting coating thereon prior to depositing the conductive coating, such as one including magnesium.

Based on findings and experimental observations, it is postulated that fullerenes and other nucleation promoting materials, as will be explained further herein, act as nucleation sites for the deposition of a conductive coating including magnesium. For example, in cases where magnesium is deposited using an evaporation process on a fullerene treated surface, the fullerene molecules act as nucleation sites that promote formation of stable nuclei for magnesium deposition. Less than a monolayer of fullerene or other nucleation promoting material may be provided on the treated surface to act as nucleation sites for deposition of magnesium in some cases. As will be understood, treating the surface by depositing several monolayers of a nucleation promoting material may result in a higher number of nucleation sites, and thus a higher initial sticking probability.

It will also be appreciated that an amount of fullerene or other material deposited on a surface may be more, or less, than one monolayer. For example, the surface may be treated by depositing 0.1 monolayer, 1 monolayer, 10 monolayers, or more of a nucleation promoting material or a nucleation inhibiting material. As used herein, depositing 1 monolayer of a material refers to an amount of the material to cover a desired area of a surface with a single layer of constituent molecules or atoms of the material. Similarly, as used herein, depositing 0.1 monolayer of a material refers to an amount of the material to cover 10% of a desired area of a surface with a single layer of constituent molecules or atoms of the material. Due to, for example, possible stacking or clustering of molecules or atoms, an actual thickness of a deposited material may be non-uniform. For example, depositing 1 monolayer of a material may result in some regions of a surface being uncovered by the material, while other regions of the surface may have multiple atomic or molecular layers deposited thereon.

As used herein, the term “fullerene” refers to a material including carbon molecules. Examples of fullerene molecules include carbon cage molecules including a three-dimensional skeleton that includes multiple carbon atoms, which form a closed shell, and which can be spherical or semi-spherical in shape. A fullerene molecule can be designated as C_(n), where n is an integer corresponding to a number of carbon atoms included in a carbon skeleton of the fullerene molecule. Examples of fullerene molecules include C_(n), where n is in the range of 50 to 250, such as C₆₀, C₇₀, C₇₂, C₇₄, C₇₆, C₇₈, C₈₀, C₈₂, and C₈₄. Additional examples of fullerene molecules include carbon molecules in a tube or cylindrical shape, such as single-walled carbon nanotubes and multi-walled carbon nanotubes.

FIG. 4 illustrates an embodiment of a device in which a nucleation promoting coating 160 is deposited prior to the deposition of a conductive coating 440. As illustrated in FIG. 4, the nucleation promoting coating 160 is deposited over regions of the substrate 100 that are uncovered by a nucleation inhibiting coating 140. Accordingly, when the conductive coating 440 is deposited, the conductive coating 440 forms preferentially over the nucleation promoting coating 160. For example, an initial deposition rate of a material of the conductive coating 440 on a surface of the nucleation promoting coating 160 may be at least or greater than about 80 times, at least or greater than about 100 times, at least or greater than about 200 times, at least or greater than about 500 times, at least or greater than about 700 times, at least or greater than about 1000 times, at least or greater than about 1500 times, at least or greater than about 1700 times, or at least or greater than about 2000 times an initial deposition rate of the material on a surface of the nucleation inhibiting coating 140. In general, the nucleation promoting coating 160 may be deposited on the substrate 100 prior to, or following, the deposition of the nucleation inhibiting coating 140. Various processes for selectively depositing a material on a surface may be used to deposit the nucleation promoting coating 160 including, but not limited to, evaporation (including thermal evaporation and electron beam evaporation), photolithography, printing (including ink or vapor jet printing, reel-to-reel printing, and micro-contact transfer printing), OVPD, LITI patterning, and combinations thereof.

FIGS. 5A-5C illustrate a process for depositing a conductive coating onto a surface of a substrate in one embodiment.

In FIG. 5A, a surface 102 of a substrate 100 is treated by depositing a nucleation inhibiting coating 140 thereon. Specifically, in the illustrated embodiment, deposition is achieved by evaporating a source material inside a source 120, and directing the evaporated source material towards the surface 102 to be deposited thereon. The general direction in which the evaporated flux is directed towards the surface 102 is indicated by arrow 122. As illustrated, deposition of the nucleation inhibiting coating 140 may be performed using an open mask or without a mask, such that the nucleation inhibiting coating 140 substantially covers the entire surface 102 to produce a treated surface 142. Alternatively, the nucleation inhibiting coating 140 may be selectively deposited onto a region of the surface 102 using, for example, a selective deposition technique described above.

While the nucleation inhibiting coating 140 is illustrated as being deposited by evaporation, it will be appreciated that other deposition and surface coating techniques may be used, including but not limited to spin coating, dip coating, printing, spray coating, OVPD, LITI patterning, physical vapor deposition (PVD) (including sputtering), chemical vapor deposition (CVD), and combinations thereof.

In FIG. 5B, a shadow mask 110 is used to selectively deposit a nucleation promoting coating 160 on the treated surface 142. As illustrated, an evaporated source material travelling from the source 120 is directed towards the substrate 100 through the mask 110. The mask includes an aperture or slit 112 such that a portion of the evaporated source material incident on the mask 110 is prevented from traveling past the mask 110, and another portion of the evaporated source material directed through the aperture 112 of the mask 110 selectively deposits onto the treated surface 142 to form the nucleation promoting coating 160. Accordingly, a patterned surface 144 is produced upon completing the deposition of the nucleation promoting coating 160.

FIG. 5C illustrates a stage of depositing a conductive coating 440 onto the patterned surface 144. The conductive coating 440 may include, for example, pure or substantially pure magnesium. As will be explained further below, a material of the conductive coating 440 exhibits a relatively low initial sticking coefficient with respect to the nucleation inhibiting coating 140 and a relatively high initial sticking coefficient with respect to the nucleation promoting coating 160. Accordingly, the deposition may be performed using an open mask or without a mask to selectively deposit the conductive coating 440 onto regions of the substrate 100 where the nucleation promoting coating 160 is present. As illustrated in FIG. 5C, an evaporated material of the conductive coating 440 that is incident on a surface of the nucleation inhibiting coating 140 may be largely or substantially prevented from being deposited onto the nucleation inhibiting coating 140.

FIGS. 5D-5F illustrate a process for depositing a conductive coating onto a surface of a substrate in another embodiment.

In FIG. 5D, a nucleation promoting coating 160 is deposited on a surface 102 of a substrate 100. For example, the nucleation promoting coating 160 may be deposited by thermal evaporation using an open mask or without a mask. Alternatively, other deposition and surface coating techniques may be used, including but not limited to spin coating, dip coating, printing, spray coating, OVPD, LITI patterning, PVD (including sputtering), CVD, and combinations thereof.

In FIG. 5E, a nucleation inhibiting coating 140 is selectively deposited over a region of the nucleation promoting coating 160 using a shadow mask 110. Accordingly, a patterned surface is produced upon completing the deposition of the nucleation inhibiting coating 140. Then in FIG. 5F, a conductive coating 440 is deposited onto the patterned surface using an open mask or a mask-free deposition process, such that the conductive coating 440 is formed over exposed regions of the nucleation promoting coating 160.

In the foregoing embodiments, it will be appreciated that the conductive coating 440 formed by the processes may be used as an electrode or a conductive structure for an electronic device. For example, the conductive coating 440 may be an anode or a cathode of an organic opto-electronic device, such as an OLED device or an organic photovoltaic (OPV) device. In addition, the conductive coating 440 may also be used as an electrode for opto-electronic devices including quantum dots as an active layer material. For example, such a device may include an active layer disposed between a pair of electrodes with the active layer including quantum dots. The device may be, for example, an electroluminescent quantum dot display device in which light is emitted from the quantum dot active layer as a result of current provided by the electrodes. The conductive coating 440 may also be a busbar or an auxiliary electrode for any of the foregoing devices.

Accordingly, it will be appreciated that the substrate 100 onto which various coatings are deposited may include one or more additional organic and/or inorganic layers not specifically illustrated or described in the foregoing embodiments. For example, in the case of an OLED device, the substrate 100 may include one or more electrodes (e.g., an anode and/or a cathode), charge injection and/or transport layers, and an electroluminescent layer. The substrate 100 may further include one or more transistors and other electronic components such as resistors and capacitors, which are included in an active-matrix or a passive-matrix OLED device. For example, the substrate 100 may include one or more top-gate thin-film transistors (TFTs), one or more bottom-gate TFTs, and/or other TFT structures. A TFT may be an n-type TFT or a p-type TFT. Examples of TFT structures include those including amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), and low-temperature polycrystalline silicon (LTPS).

The substrate 100 may also include a base substrate for supporting the above-identified additional organic and/or inorganic layers. For example, the base substrate may be a flexible or rigid substrate. The base substrate may include, for example, silicon, glass, metal, polymer (e.g., polyimide), sapphire, or other materials suitable for use as the base substrate.

The surface 102 of the substrate 100 may be an organic surface or an inorganic surface. For example, if the conductive coating 440 is for use as a cathode of an OLED device, the surface 102 may be a top surface of a stack of organic layers (e.g., a surface of an electron injection layer). In another example, if the conductive coating 440 is for use as an auxiliary electrode of a top-emission OLED device, the surface 102 may be a top surface of an electrode (e.g., a common cathode). Alternatively, such an auxiliary electrode may be formed directly beneath a transmissive electrode on top of a stack of organic layers.

FIG. 6 illustrates an electroluminescent (EL) device 600 according to one embodiment. The EL device 600 may be, for example, an OLED device or an electroluminescent quantum dot device. In one embodiment, the device 600 is an OLED device including a base substrate 616, an anode 614, organic layers 630, and a cathode 602. In the illustrated embodiment, the organic layers 630 include a hole injection layer 612, a hole transport layer 610, an electroluminescent layer 608, an electron transport layer 606, and an electron injection layer 604.

The hole injection layer 612 may be formed using a hole injection material which generally facilitates the injection of holes by the anode 614. The hole transport layer 610 may be formed using a hole transport material, which is generally a material that exhibits high hole mobility.

The electroluminescent layer 608 may be formed, for example, by doping a host material with an emitter material. The emitter material may be a fluorescent emitter, a phosphorescent emitter, or a TADF emitter, for example. A plurality of emitter materials may also be doped into the host material to form the electroluminescent layer 608.

The electron transport layer 606 may be formed using an electron transport material which generally exhibits high electron mobility. The electron injection layer 604 may be formed using an electron injection material, which generally acts to facilitate the injection of electrons by the cathode 602.

It will be understood that the structure of the device 600 may be varied by omitting or combining one or more layers. Specifically, one or more of the hole injection layer 612, the hole transport layer 610, the electron transport layer 606, and the electron injection layer 604 may be omitted from the device structure. One or more additional layers may also be present in the device structure. Such additional layers include, for example, a hole blocking layer, an electron blocking layer, and additional charge transport and/or injection layers. Each layer may further include any number of sub-layers, and each layer and/or sub-layer may include various mixtures and composition gradients. It will also be appreciated that the device 600 may include one or more layers containing inorganic and/or organo-metallic materials, and is not limited to devices composed solely of organic materials. For example, the device 600 may include quantum dots.

The device 600 may be connected to a power source 620 for supplying current to the device 600.

In another embodiment where the device 600 is an EL quantum dot device, the EL layer 608 generally includes quantum dots, which emit light when current is supplied.

FIG. 7 is a flow diagram outlining stages of fabricating an OLED device according to one embodiment. In 704, organic layers are deposited on a target surface. For example, the target surface may be a surface of an anode that has been deposited on top of a base substrate, which may include, for example, glass, polymer, and/or metal foil. As discussed above, the organic layers may include, for example, a hole injection layer, a hole transport layer, an electroluminescence layer, an electron transport layer, and an electron injection layer. A nucleation inhibiting coating is then deposited on top of the organic layers in stage 706 using a selective deposition or patterning process. In stage 708, a nucleation promoting coating is selectively deposited on the nucleation inhibiting coating to produce a patterned surface. For example, the nucleation promoting coating and the nucleation inhibiting coating may be selectively deposited by evaporation using a mask, micro-contact transfer printing process, photolithography, printing (including ink or vapor jet printing and reel-to-reel printing), OVPD, or LITI patterning. A conductive coating is then deposited on the patterned surface using an open mask or a mask-free deposition process in stage 710. The conductive coating may serve as a cathode or another conductive structure of the OLED device.

Referring next to FIGS. 8 and 9A-9D, a process for fabricating an OLED device according to another embodiment is provided. FIG. 8 is a flow diagram outlining stages for fabricating the OLED device, and FIGS. 9A-9D are schematic diagrams illustrating the device at each stage of the process. In stage 804, organic layers 920 are deposited on a target surface 912 using a source 991. In the illustrated embodiment, the target surface 912 is a surface of an anode 910 that has been deposited on top of a base substrate 900. The organic layers 920 may include, for example, a hole injection layer, a hole transport layer, an electroluminescence layer, an electron transport layer, and an electron injection layer. A nucleation promoting coating 930 is then deposited on top of the organic layers 920 in stage 806 using a source 993 and an open mask, or without a mask. In stage 808, a nucleation inhibiting coating 940 is selectively deposited on the nucleation promoting coating 930 using a mask 980 and a source 995, thereby producing a patterned surface. A conductive coating 950 is then deposited on the patterned surface using an open mask or a mask-free deposition process in stage 810, such that the conductive coating 950 is deposited on regions of the nucleation promoting coating 930 which are not covered by the nucleation inhibiting coating 940.

Referring next to FIGS. 10 and 11A-11D, a process for fabricating an OLED device according to yet another embodiment is provided. FIG. 10 is a flow diagram outlining stages for fabricating the OLED device, and FIGS. 11A-11D are schematic diagrams illustrating the stages of such a process. In stage 1004, organic layers 1120 are deposited on a target surface 1112 using a source 1191. In the illustrated embodiment, the target surface 1112 is a surface of an anode 1110 that has been deposited on top of a base substrate 1100. The organic layers 1120 may include, for example, a hole injection layer, a hole transport layer, an electroluminescence layer, an electron transport layer, and an electron injection layer. A nucleation inhibiting coating 1130 is then deposited on top of the organic layers 1120 in stage 1006 using a mask 1180 and a source 1193, such that the nucleation inhibiting coating 1130 is selectively deposited on a region of a surface of the organic layers 1120 that is exposed through an aperture of the mask 1180. In stage 1008, a nucleation promoting coating 1140 is selectively deposited using a mask 1182 and a source 1195. In the illustrated embodiment, the nucleation promoting coating 1140 is shown as being deposited over regions of the surface of the organic layers 1120 which are not covered by the nucleation inhibiting coating 1130, thereby producing a patterned surface. A conductive coating 1150 is then deposited on the patterned surface using an open mask or a mask-free deposition process in stage 1010, resulting in the conductive coating 1150 being deposited on a surface of the nucleation promoting coating 1140 while leaving a surface of the nucleation inhibiting coating 1130 substantially free of a material of the conductive coating 1150.

Referring next to FIGS. 12 and 13A-13D, a process for fabricating an OLED device according to yet another embodiment is provided. FIG. 12 is a flow diagram outlining stages for fabricating the OLED device, and FIGS. 13A-13D are schematic diagrams illustrating the stages of such a process. In stage 1204, organic layers 1320 are deposited on a target surface 1312 using a source 1391. In the illustrated embodiment, the target surface 1312 is a surface of an anode 1310 that has been deposited on top of a base substrate 1300. The organic layers 1320 may include, for example, a hole injection layer, a hole transport layer, an electroluminescence layer, an electron transport layer, and an electron injection layer. A nucleation promoting coating 1330 is then deposited on top of the organic layers 1320 in stage 1206 using a mask 1380 and a source 1393, such that the nucleation promoting coating 1330 is selectively deposited on a region of a surface of the organic layers 1320 that is exposed through an aperture of the mask 1380. In stage 1208, a nucleation inhibiting layer 1340 is selectively deposited using a mask 1382 and a source 1395. In the illustrated embodiment, the nucleation inhibiting coating 1340 is illustrated as being deposited over regions of the surface of the organic layers 1320 which are not covered by the nucleation promoting coating 1330, thereby producing a patterned surface. A conductive coating 1350 is then deposited on the patterned surface using an open mask or a mask-free deposition process in stage 1210, resulting in the conductive coating 1350 being deposited on a surface of the nucleation promoting coating 1330 while leaving a surface of the nucleation inhibiting coating 1340 substantially free of a material of the conductive coating 1350. The conductive coating 1350 formed in this manner may serve as an electrode (e.g., a cathode).

In accordance with the above-described embodiments, a conductive coating may be selectively deposited on target regions (e.g., non-emissive regions) using an open mask or a mask-free deposition process, through the use of a nucleation inhibiting coating or a combination of nucleation inhibiting and nucleation promoting coatings. By contrast, the lack of sufficient selectivity in an open mask or a mask-free deposition process would result in deposition of a conductive material beyond target regions and over emissive regions, which is undesired since the presence of such material over the emissive regions generally contributes to attenuation of light and thus a decrease in an EQE of an OLED device. Moreover, by providing high selectivity in depositing a conductive coating on target regions, the conductive coating can serve as an electrode with a sufficient thickness to achieve a desired conductivity in an OLED device. For example, the high selectivity provided by the above-described embodiments allows deposition of an auxiliary electrode having a high aspect ratio that remains confined to regions between neighbouring pixels or sub-pixels. By contrast, the lack of sufficient selectivity in forming a thick electrode in an open mask or a mask-free deposition process would result in deposition of a thick coating of a conductive material over both emissive and non-emissive regions, thus substantially decreasing a performance of a resulting OLED device.

For the sake of simplicity and clarity, details of deposited materials including thickness profiles and edge profiles have been omitted from the process diagrams.

The formation of thin films during vapor deposition on a surface of a substrate involves processes of nucleation and growth. During initial stages of film formation, a sufficient number of vapor monomers (e.g., atoms or molecules) typically condense from a vapor phase to form initial nuclei on the surface. As vapor monomers continue to impinge upon the surface, a size and density of these initial nuclei increase to form small clusters or islands. After reaching a saturation island density, adjacent islands typically will start to coalesce, increasing an average island size, while decreasing an island density. Coalescence of adjacent islands continues until a substantially closed film is formed.

There can be three basic growth modes for the formation of thin films: 1) island (Volmer-Weber), 2) layer-by-layer (Frank-van der Merwe), and 3) Stranski-Krastanov. Island growth typically occurs when stable clusters of monomers nucleate on a surface and grow to form discrete islands. This growth mode occurs when the interactions between the monomers is stronger than that between the monomers and the surface.

The nucleation rate describes how many nuclei of a critical size form on a surface per unit time. During initial stages of film formation, it is unlikely that nuclei will grow from direct impingement of monomers on the surface, since the density of nuclei is low, and thus the nuclei cover a relatively small fraction of the surface (e.g., there are large gaps/spaces between neighboring nuclei). Therefore, the rate at which critical nuclei grow typically depends on the rate at which adsorbed monomers (e.g., adatoms) on the surface migrate and attach to nearby nuclei.

After adsorption of an adatom on a surface, the adatom may either desorb from the surface, or may migrate some distance on the surface before either desorbing, interacting with other adatoms to form a small cluster, or attach to a growing nuclei. An average amount of time that an adatom remains on the surface after initial adsorption is given by:

$\tau_{s} = {\frac{1}{v}{\exp\left( \frac{E_{des}}{kT} \right)}}$

In the above equation, visa vibrational frequency of the adatom on the surface, k is the Boltzmann constant, T is temperature, and E_(des) is an energy involved to desorb the adatom from the surface. From this equation it is noted that the lower the value of E_(des) the easier it is for the adatom to desorb from the surface, and hence the shorter the time the adatom will remain on the surface. A mean distance an adatom can diffuse is given by,

$X = {a_{0}{\exp\left( \frac{E_{des} - E_{S}}{2{kT}} \right)}}$ where a₀ is a lattice constant and E_(S) is an activation energy for surface diffusion. For low values of E_(des) and/or high values of E_(S) the adatom will diffuse a shorter distance before desorbing, and hence is less likely to attach to a growing nuclei or interact with another adatom or cluster of adatoms.

During initial stages of film formation, adsorbed adatoms may interact to form clusters, with a critical concentration of clusters per unit area being given by,

$\frac{N_{i}}{n_{0}} = {{\frac{N_{1}}{n_{0}}}^{i}\mspace{14mu}{\exp\left( \frac{E_{i}}{kT} \right)}}$

where E_(i) is an energy involved to dissociate a critical cluster containing i adatoms into separate adatoms, n₀ is a total density of adsorption sites, and N₁ is a monomer density given by: N₁={dot over (R)}τ_(s) where {dot over (R)} is a vapor impingement rate. Typically i will depend on a crystal structure of a material being deposited and will determine the critical cluster size to form a stable nucleus.

A critical monomer supply rate for growing clusters is given by the rate of vapor impingement and an average area over which an adatom can diffuse before desorbing:

${\overset{.}{R}X^{2}} = {a_{0}^{2}{\exp\left( \frac{E_{des} - E_{S}}{kT} \right)}}$

The critical nucleation rate is thus given by the combination of the above equations:

${\overset{.}{N}}_{i} = {\overset{.}{R}a_{0}^{2}{n_{0}\left( \frac{\overset{.}{R}}{{vn}_{0}} \right)}^{i}\mspace{14mu}{\exp\left( \frac{{\left( {i + 1} \right)E_{des}} - E_{S} + E_{i}}{kT} \right)}}$

From the above equation it is noted that the critical nucleation rate will be suppressed for surfaces that have a low desorption energy for adsorbed adatoms, a high activation energy for diffusion of an adatom, are at high temperatures, or are subjected to low vapor impingement rates.

Sites of substrate heterogeneities, such as defects, ledges or step edges, may increase E_(des), leading to a higher density of nuclei observed at such sites. Also, impurities or contamination on a surface may also increase E_(des), leading to a higher density of nuclei. For vapor deposition processes conducted under high vacuum conditions, the type and density of contaminates on a surface is affected by a vacuum pressure and a composition of residual gases that make up that pressure.

Under high vacuum conditions, a flux of molecules that impinge on a surface (per cm²-sec) is given by:

$\Phi = {3.513 \times 10^{22}\frac{P}{MT}}$ where P is pressure, and M is molecular weight. Therefore, a higher partial pressure of a reactive gas, such as H₂O, can lead to a higher density of contamination on a surface during vapor deposition, leading to an increase in E_(des) and hence a higher density of nuclei.

A useful parameter for characterizing nucleation and growth of thin films is the sticking probability given by:

$S = \frac{N_{ads}}{N_{total}}$ where N_(ads) is a number of adsorbed monomers that remain on a surface (e.g., are incorporated into a film) and N_(total) is a total number of impinging monomers on the surface. A sticking probability equal to 1 indicates that all monomers that impinge the surface are adsorbed and subsequently incorporated into a growing film. A sticking probability equal to 0 indicates that all monomers that impinge the surface are desorbed and subsequently no film is formed on the surface. A sticking probability of metals on various surfaces can be evaluated using various techniques of measuring the sticking probability, such as a dual quartz crystal microbalance (QCM) technique as described by Walker et al., J. Phys. Chem. C 2007, 111, 765 (2006) and in the Examples section below.

As the density of islands increases (e.g., increasing average film thickness), a sticking probability may change. For example, a low initial sticking probability may increase with increasing average film thickness. This can be understood based on a difference in sticking probability between an area of a surface with no islands (bare substrate) and an area with a high density of islands. For example, a monomer that impinges a surface of an island may have a sticking probability close to 1.

An initial sticking probability S₀ can therefore be specified as a sticking probability of a surface prior to the formation of any significant number of critical nuclei. One measure of an initial sticking probability can involve a sticking probability of a surface for a material during an initial stage of deposition of the material, where an average thickness of the deposited material across the surface is at or below threshold value. In the description of some embodiments, a threshold value for an initial sticking probability can be specified as 1 nm. An average sticking probability is then given by: S=S₀(1−A _(nuc))+S_(nuc)(A _(nuc)) where S_(nuc) is a sticking probability of an area covered by islands, and A_(nuc) is a percentage of an area of a substrate surface covered by islands.

Suitable materials for use to form a nucleation inhibiting coating include those exhibiting or characterized as having an initial sticking probability for a material of a conductive coating of no greater than or less than about 0.1 (or 10%) or no greater than or less than about 0.05, and, more particularly, no greater than or less than about 0.03, no greater than or less than about 0.02, no greater than or less than about 0.01, no greater than or less than about 0.08, no greater than or less than about 0.005, no greater than or less than about 0.003, no greater than or less than about 0.001, no greater than or less than about 0.0008, no greater than or less than about 0.0005, or no greater than or less than about 0.0001. Suitable materials for use to form a nucleation promoting coating include those exhibiting or characterized as having an initial sticking probability for a material of a conductive coating of at least about 0.6 (or 60%), at least about 0.7, at least about 0.75, at least about 0.8, at least about 0.9, at least about 0.93, at least about 0.95, at least about 0.98, or at least about 0.99.

Suitable nucleation inhibiting materials include organic materials, such as small molecule organic materials and organic polymers. Examples of suitable organic materials include polycyclic aromatic compounds including organic molecules which may optionally include one or more heteroatoms, such as nitrogen (N), sulfur (S), oxygen (O), phosphorus (P), and aluminum (Al). In some embodiments, a polycyclic aromatic compound includes organic molecules each including a core moiety and at least one terminal moiety bonded to the core moiety. A number of terminal moieties may be 1 or more, 2 or more, 3 or more, or 4 or more. In the case of 2 or more terminal moieties, the terminal moieties may be the same or different, or a subset of the terminal moieties may be the same but different from at least one remaining terminal moiety. In some embodiments, at least one terminal moiety is, or includes, a biphenylyl moiety represented by one of the chemical structures (I-a), (I-b), and (Ic) as follows:

wherein the dotted line indicates a bond formed between the biphenylyl moiety and the core moiety. In general, the biphenylyl moiety represented by (I-a), (I-b) and (I-c) may be unsubstituted or may be substituted by having one or more of its hydrogen atoms replaced by one or more substituent groups. In the moiety represented by (I-a), (I-b), and (I-c), R_(a) and R_(b) independently represent the optional presence of one or more substituent groups, wherein R_(a) may represent mono, di, tri, or tetra substitution, and R_(b) may represent mono, di, tri, tetra, or penta substitution. For example, one or more substituent groups, R_(a) and R_(b), may independently be selected from: deutero, fluoro, alkyl including C₁-C₄ alkyl, cycloalkyl, arylalkyl, silyl, aryl, heteroaryl, fluoroalkyl, and any combinations thereof. Particularly, one or more substituent groups, R_(a) and R_(b), may be independently selected from: methyl, ethyl, t-butyl, trifluoromethyl, phenyl, methylphenyl, dimethylphenyl, trimethylphenyl, t-butylphenyl, biphenylyl, methylbiphenylyl, dimethylbiphenylyl, trimethylbiphenylyl, t-butylbiphenylyl, fluorophenyl, difluorophenyl, trifluorophenyl, polyfluorophenyl, fluorobiphenylyl, difluorobiphenylyl, trifluorobiphenylyl, and polyfluorobiphenylyl. Without wishing to be bound by a particular theory, the presence of an exposed biphenylyl moiety on a surface may serve to adjust or tune a surface energy (e.g., a desorption energy) to lower an affinity of the surface towards deposition of a conductive material such as magnesium. Other moieties and materials that yield a similar tuning of a surface energy to inhibit deposition of magnesium may be used to form a nucleation inhibiting coating.

In another embodiment, at least one terminal moiety is, or includes, a phenyl moiety represented by the structure (I-d) as follows:

wherein the dotted line indicates a bond formed between the phenyl moiety and the core moiety. In general, the phenyl moiety represented by (I-d) may be unsubstituted or may be substituted by having one or more of its hydrogen atoms replaced by one or more substituent groups. In the moiety represented by (I-d), R_(c) represents the optional presence of one or more substituent groups, wherein R_(c) may represent mono, di, tri, tetra, or penta substitution. One or more substituent groups, R_(c), may be independently selected from: deutero, fluoro, alkyl including C₁-C₄ alkyl, cycloalkyl, silyl, fluoroalkyl, and any combinations thereof. Particularly, one or more substituent groups, R_(c), may be independently selected from: methyl, ethyl, t-butyl, fluoromethyl, bifluoromethyl, trifluoromethyl, fluoroethyl, and polyfluoroethyl.

In yet another embodiment, at least one terminal moiety is, or includes, a polycyclic aromatic moiety including fused ring structures, such as fluorene moieties or phenylene moieties (including those containing multiple (e.g., 3, 4, or more) fused benzene rings). Examples of such moieties include spirobifluorene moiety, triphenylene moiety, diphenylfluorene moiety, dimethylfluorene moiety, difluorofluorene moiety, and any combinations thereof.

In some embodiments, a polycyclic aromatic compound includes organic molecules represented by at least one of chemical structures (II), (III), and (IV) as follows:

In (II), (III), and (IV), C represents a core moiety, and T₁, T₂, and T₃ represent terminal moieties bonded to the core moiety. Although 1, 2, and 3 terminal moieties are depicted in (II), (III), and (IV), it should be understood that more than 3 terminal moieties also may be included.

In some embodiments, C is, or includes, a heterocyclic moiety, such as a heterocyclic moiety including one or more nitrogen atoms, for which an example is a triazole moiety. In some embodiments, C is, or includes, a metal atom (including transition and post-transition atoms), such as an aluminum atom, a copper atom, an iridium atom, and/or a platinum atom. In some embodiments, C is, or includes, a nitrogen atom, an oxygen atom, and/or a phosphorus atom. In some embodiments, C is, or includes, a cyclic hydrocarbon moiety, which may be aromatic. In some embodiments, C is, or includes, a substituted or unsubstituted alkyl, which may be branched or unbranched, a cycloalkynyl (including those containing between 1 and 7 carbon atoms), an alkenyl, an alkynyl, an aryl (including phenyl, naphthyl, thienyl, and indolyl), an arylalkyl, a heterocyclic moiety (including cyclic amines such as morpholino, piperdino and pyrolidino), a cyclic ether moiety (such as tetrahydrofuran and tetrahydropyran moieties), a heteroaryl (including pyrrole, furan, thiophene, imidazole, oxazole, thiazole, triazole, pyrazole, pyridine, pyrazine, pyrimidine, polycyclic heteroaromatic moieties, and dibenzylthiophenyl), fluorene moieties, silyl, and any combinations thereof.

In (II), (III), and (IV), T₁ is, or includes, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above. The moiety, T₁, may be directly bonded to the core moiety, or may be bonded to the core moiety via a linker moiety. Examples of a linker moiety include —O— (where O denotes an oxygen atom), —S— (where S denotes a sulfur atom), and cyclic or acyclic hydrocarbon moieties including 1, 2, 3, 4, or more carbon atoms, and which may be unsubstituted or substituted, and which may optionally include one or more heteroatoms. The bond between the core moiety and one or more terminal moieties may be a covalent bond or a bond formed between a metallic element and an organic element, particularly in the case of organometallic compounds.

In (III), T₁ and T₂ may be the same or different, as long as at least T₁ is, or includes, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above. For example, each of T₁ and T₂ may be, or may include, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above. As another example, T₁ is, or includes, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above, while T₂ may lack such a moiety. In some embodiments, T₂ is, or includes, a cyclic hydrocarbon moiety, which may be aromatic, which may include a single ring structure or may be polycyclic, which may be substituted or unsubstituted, and which may be directly bonded to the core moiety, or may be bonded to the core moiety via a linker moiety. In some embodiments, T₂ is, or includes, a heterocyclic moiety, such as a heterocyclic moiety including one or more nitrogen atoms, which may include a single ring structure or may be polycyclic, which may be substituted or unsubstituted, and which may be directly bonded to the core moiety, or may be bonded to the core moiety via a linker moiety. In some embodiments, T₂ is, or includes, an acyclic hydrocarbon moiety, which may be unsubstituted or substituted, which may optionally include one or more heteroatoms, and which may be directly bonded to the core moiety, or may be bonded to the core moiety via a linker moiety. In some embodiments where T₁ and T₂ are different, T₂ may be selected from moieties having sizes comparable to T₁. Specifically, T₂ may be selected from the above-listed moieties having molecular weights no greater than about 2 times, no greater than about 1.9 times, no greater than about 1.7 times, no greater than about 1.5 times, no greater than about 1.2 times, or no greater than about 1.1 times a molecular weight of T₁. Without wishing to be bound by a particular theory, it is postulated that, when the terminal moiety T₂ is included which is different from or lacks a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above, a comparable size of T₂ with respect to T₁ may promote exposure of T₁ on a surface, in contrast to bulky terminal groups that may hinder exposure of T₁ due to molecular stacking, steric hindrance, or a combination of such effects.

In (IV), T₁, T₂, and T₃ may be the same or different, as long as at least T₁ is, or includes, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above. For example, each of T₁, T₂, and T₃ may be, or may include, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above. As another example, each of T₁ and T₂ may be, or may include, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above, while T₃ may lack such a moiety. As another example, each of T₁ and T₃ may be, or may include, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above, while T₂ may lack such a moiety. As a further example, T₁ is, or includes, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above, while both T₂ and T₃ may lack such a moiety. In some embodiments, at least one T₂ and T₃ is, or includes, a cyclic hydrocarbon moiety, which may be aromatic, which may include a single ring structure or may be polycyclic, which may be substituted or unsubstituted, and which may be directly bonded to the core moiety, or may be bonded to the core moiety via a linker moiety. In some embodiments, at least one T₂ and T₃ is, or includes, a heterocyclic moiety, such as a heterocyclic moiety including one or more nitrogen atoms, which may include a single ring structure or may be polycyclic, which may be substituted or unsubstituted, and which may be directly bonded to the core moiety, or may be bonded to the core moiety via a linker moiety. In some embodiments, at least one T₂ and T₃ is, or includes, an acyclic hydrocarbon moiety, which may be unsubstituted or substituted, which may optionally include one or more heteroatoms, and which may be directly bonded to the core moiety, or may be bonded to the core moiety via a linker moiety. In some embodiments where T₁, T₂, and T₃ are different, T₂ and T₃ may be selected from moieties having sizes comparable to T₁. Specifically, T₂ and T₃ may be selected from the above-listed moieties having molecular weights no greater than about 2 times, no greater than about 1.9 times, no greater than about 1.7 times, no greater than about 1.5 times, no greater than about 1.2 times, or no greater than about 1.1 times a molecular weight of T₁. Without wishing to be bound by a particular theory, it is postulated that, when the terminal moieties T₂ and T₃ are included which are different from or lacks a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above, a comparable size of T₂ and T₃ with respect to T₁ may promote exposure of T₁ on a surface, in contrast to bulky terminal groups that may hinder exposure of T₁ due to molecular stacking, steric hindrance, or a combination of such effects.

Suitable nucleation inhibiting materials include polymeric materials. Examples of such polymeric materials include: fluoropolymers, including but not limited to perfluorinated polymers and polytetrafluoroethylene (PTFE); polyvinylbiphenyl; polyvinylcarbazole (PVK); and polymers formed by polymerizing a plurality of the polycyclic aromatic compounds as described above. In another example, polymeric materials include polymers formed by polymerizing a plurality of monomers, wherein at least one of the monomers includes a terminal moiety that is, or includes, a moiety represented by (I-a), (I-b), (I-c), or (I-d), or a polycyclic aromatic moiety including fused ring structures as described above.

FIGS. 14 and 15 illustrates an OLED device 1500 according to one embodiment. Specifically, FIG. 14 shows a top view of the OLED device 1500, and FIG. 15 illustrates a cross-sectional view of a structure of the OLED device 1500. In FIG. 14, a cathode 1550 is illustrated as a single monolithic or continuous structure having or defining a plurality of apertures or holes 1560 formed therein, which correspond to regions of the device 1500 where a cathode material was not deposited. This is further illustrated in FIG. 15, which shows the OLED device 1500 including a base substrate 1510, an anode 1520, organic layers 1530, a nucleation promoting coating 1540, a nucleation inhibiting coating 1570 selectively deposited over certain regions of the nucleation promoting coating 1540, and the cathode 1550 deposited over other regions of the nucleation promoting coating 1540 where the nucleation inhibiting coating 1570 is not present. More specifically, by selectively depositing the nucleation inhibiting coating 1570 to cover certain regions of a surface of the nucleation promoting coating 1540 during the fabrication of the device 1500, the cathode material is selectively deposited on exposed regions of the surface of the nucleation promoting coating 1540 using an open mask or a mask-free deposition process. The transparency or transmittance of the OLED device 1500 may be adjusted or modified by changing various parameters of an imparted pattern, such as an average size of the holes 1560 and a density of the holes 1560 formed in the cathode 1550. Accordingly, the OLED device 1500 may be a substantially transparent OLED device, which allows at least a portion of an external light incident on the OLED device to be transmitted therethrough. For example, the OLED device 1500 may be a substantially transparent OLED lighting panel. Such OLED lighting panel may be, for example, configured to emit light in one direction (e.g., either towards or away from the base substrate 1510) or in both directions (e.g., towards and away from the base substrate 1510).

FIG. 16 illustrates an OLED device 1600 according to another embodiment in which a cathode 1650 substantially covers an entire device area. Specifically, the OLED device 1600 includes a base substrate 1610, an anode 1620, organic layers 1630, a nucleation promoting coating 1640, the cathode 1650, a nucleation inhibiting coating 1660 selectively deposited over certain regions of the cathode 1650, and an auxiliary electrode 1670 deposited over other regions of the cathode 1650 where the nucleation inhibiting coating 1660 is not present.

The auxiliary electrode 1670 is electrically connected to the cathode 1650. Particularly in a top-emission configuration, it is desirable to deposit a relatively thin layer of the cathode 1650 to reduce optical interference (e.g., attenuation, reflection, diffusion, and so forth) due to the presence of the cathode 1650. However, a reduced thickness of the cathode 1650 generally increases a sheet resistance of the cathode 1650, thus reducing the performance and efficiency of the OLED device 1600. By providing the auxiliary electrode 1670 that is electrically connected to the cathode 1650, the sheet resistance and thus the IR drop associated with the cathode 1650 can be decreased. Furthermore, by selectively depositing the auxiliary electrode 1670 to cover certain regions of the device area while other regions remain uncovered, optical interference due to the presence of the auxiliary electrode 1670 may be controlled and/or reduced.

The effect of an electrode sheet resistance will now be explained with reference to FIG. 48, which shows an example of a circuit diagram for a top-emission active matrix OLED (AMOLED) pixel with a p-type TFT. In FIG. 48, a circuit 4800 includes a power supply (VDD) line 4812, a control line 4814, a gate line 4816, and a data line 4818. A driving circuit including a first TFT 4831, a second TFT 4833, and a storage capacitor 4841 is provided, and the driving circuit components are connected to the data line 4818, the gate line 4816, and the VDD line 4812 in the manner illustrated in the figure. A compensation circuit 4843 is also provided, which generally acts to compensate for any deviation in transistor properties caused by manufacturing variances or degradation of the TFTs 4831 and 4833 over time.

An OLED pixel or subpixel 4850 and a cathode 4852, which is represented as a resistor in the circuit diagram, are connected in series with the second TFT 4833 (also referred to as a “driving transistor”). The driving transistor 4833 regulates a current passed through the OLED pixel 4850 in accordance with a voltage of a charge stored in the storage capacitor 4841, such that the OLED pixel 4850 outputs a desired luminance. The voltage of the storage capacitor 4841 is set by connecting the storage capacitor 4841 to the data line 4818 via the first TFT 4831 (also referred to as a “switch transistor”).

Since the current through the OLED pixel or subpixel 4850 and the cathode 4852 is regulated based on a potential difference between a gate voltage and a source voltage of the driving transistor 4833, an increase in a sheet resistance of the cathode 4852 results in a greater IR drop, which is compensated by increasing the power supply (VDD). However, when the VDD is increased, other voltages supplied to the TFT 4833 and the OLED pixel 4850 are also increased to maintain proper operation, and thus is unfavorable.

Referring to FIG. 48, an auxiliary electrode 4854 is illustrated as a resistor connected in parallel to the cathode 4852. Since the resistance of the auxiliary electrode 4854 is substantially lower than that of the cathode 4852, a combined effective resistance of the auxiliary electrode 4854 and the cathode 4852 is lower than that of the cathode 4852 alone. Accordingly, an increase in the VDD can be mitigated by the presence of the auxiliary electrode 4854.

While the advantages of auxiliary electrodes have been explained in reference to top-emission OLED devices, it may also be advantageous to selectively deposit an auxiliary electrode over a cathode of a bottom-emission or double-sided emission OLED device. For example, while the cathode may be formed as a relatively thick layer in a bottom-emission OLED device without substantially affecting optical characteristics of the device, it may still be advantageous to form a relatively thin cathode. For example, in a transparent or semi-transparent display device, layers of the entire device including a cathode can be formed to be substantially transparent or semi-transparent. Accordingly, it may be beneficial to provide a patterned auxiliary electrode which cannot be readily detected by a naked eye from a typical viewing distance. It will also be appreciated that the described processes may be used to form busbars or auxiliary electrodes for decreasing a resistance of electrodes for devices other than OLED devices.

In some embodiments, a nucleation inhibiting coating deposited during a fabrication process may be removed by using, for example, a solvent or plasma etching after a conductive coating has been deposited.

FIG. 59A illustrates a device 5901 according to one embodiment, which includes a substrate 5910 and a nucleation inhibiting coating 5920 and a conductive coating 5915 (e.g., a magnesium coating) deposited over respective regions of a surface of the substrate 5910.

FIG. 59B illustrates a device 5902 after the nucleation inhibiting coating 5920 present in the device 5901 has been removed from the surface of the substrate 5910, such that the conductive coating 5915 remains on the substrate 5910 and regions of the substrate 5910 which were covered by the nucleation inhibiting coating 5920 are now exposed or uncovered. For example, the nucleation inhibiting coating 5920 of the device 5901 may be removed by exposing the substrate 5910 to solvent or plasma which preferentially reacts and/or etches away the nucleation inhibiting coating 5920 without substantially affecting the conductive coating 5915.

At least some of the above embodiments have been described in reference to various layers or coatings, including a nucleation promoting coating, a nucleation inhibiting coating, and a conductive coating, being formed using an evaporation process. As will be understood, an evaporation process is a type of PVD process where one or more source materials are evaporated or sublimed under a low pressure (e.g., vacuum) environment and deposited on a target surface through de-sublimation of the one or more evaporated source materials. A variety of different evaporation sources may be used for heating a source material, and, as such, it will be appreciated that the source material may be heated in various ways. For example, the source material may be heated by an electric filament, electron beam, inductive heating, or by resistive heating. In addition, such layers or coatings may be deposited and/or patterned using other suitable processes, including photolithography, printing, OVPD, LITI patterning, and combinations thereof. These processes may also be used in combination with a shadow mask to achieve various patterns.

For example, magnesium may be deposited at source temperatures up to about 600° C. to achieve a faster rate of deposition, such as about 10 to 30 nm per second or more. Referring to Table 1 below, various deposition rates measured using a Knudsen cell source to deposit substantially pure magnesium on a fullerene-treated organic surface of about 1 nm are provided. It will be appreciated that other factors may also affect a deposition rate including, but not limited to, a distance between a source and a substrate, characteristics of the substrate, presence of a nucleation promoting coating on the substrate, the type of source used and a shaping of a flux of material evaporated from the source.

TABLE 1 Magnesium Deposition Rate by Temperature Sample # Temperature (° C.) Rate (angstroms/s) 1 510 10 2 525 40 3 575 140 4 600 160

It will be appreciated by those skilled in the art that particular processing conditions used may vary depending on an equipment being used to conduct a deposition. It will also be appreciated that higher deposition rates are generally attained at higher source temperatures; however, other deposition conditions can be selected, such as, for example, by placing a substrate closer to a deposition source.

It will also be appreciated that an open mask used for deposition of any of various layers or coatings, including a conductive coating, a nucleation inhibiting coating, and a nucleation promoting coating, may “mask” or prevent deposition of a material on certain regions of a substrate. However, unlike a fine metal mask (FMM) used to form relatively small features with a feature size on the order of tens of microns or smaller, a feature size of an open mask is generally comparable to the size of an OLED device being manufactured. For example, the open mask may mask edges of a display device during manufacturing, which would result in the open mask having an aperture that approximately corresponds to a size of the display device (e.g. about 1 inch for micro-displays, about 4-6 inches for mobile displays, about 8-17 inches for laptop or tablet displays, and so forth). For example, the feature size of an open mask may be on the order of about 1 cm or greater.

FIG. 16B illustrates an example of an open mask 1731 having or defining an aperture 1734 formed therein. In the illustrated example, the aperture 1734 of the mask 1731 is smaller than a size of a device 1721, such that, when the mask 1731 is overlaid, the mask 1731 covers edges of the device 1721. Specifically, in the illustrated embodiments, all or substantially all emissive regions or pixels 1723 of the device 1721 are exposed through the aperture 1734, while an unexposed region 1727 is formed between outer edges 1725 of the device 1721 and the aperture 1734. As would be appreciated, electrical contacts or other device components may be located in the unexposed region 1727 such that these components remain unaffected through the open mask deposition process.

FIG. 16C illustrates another example of an open mask 1731 where an aperture 1734 of the mask 1731 is smaller than that of FIG. 16B, such that the mask 1731 covers at least some emissive regions or pixels 1723 of a device 1721 when overlaid. Specifically, outer-most pixels 1723′ are illustrated as being located within an unexposed region 1727 of the device 1721 formed between the aperture 1734 of the mask 1731 and outer edges 1725 of the device 1721.

FIG. 16D illustrates yet another example of an open mask 1731 wherein an aperture 1734 of the mask 1731 defines a pattern, which covers some pixels 1723′ while exposing other pixels 1723 of a device 1721. Specifically, the pixels 1723′ located within an unexposed region 1727 of the device 1721 (formed between the aperture 1734 and outer edges 1725) are masked during the deposition process to inhibit a vapor flux from being incident on the unexposed region 1727.

While outer-most pixels have been illustrated as being masked in the examples of FIGS. 16B-16D, it will be appreciated that an aperture of an open mask may be shaped to mask other emissive and non-emissive regions of a device. Furthermore, while an open mask has been illustrated in the foregoing examples as having one aperture, the open mask may also include additional apertures for exposing multiple regions of a substrate or a device.

FIG. 16E illustrates another example of an open mask 1731, where the mask 1731 has or defines a plurality of apertures 1734 a-1734 d. The apertures 1734 a-1734 d are positioned such that they selectively expose certain regions of a device 1721 while masking other regions. For example, certain emissive regions or pixels 1723 are exposed through the apertures 1734 a-d, while other pixels 1723′ located within an unexposed region 1727 are masked.

In various embodiments described herein, it will be understood that the use of an open mask may be omitted, if desired. Specifically, an open mask deposition process described herein may alternatively be conducted without the use of a mask, such that an entire target surface is exposed.

Although certain processes have been described with reference to evaporation for purposes of depositing a nucleation promoting material, a nucleation inhibiting material, and magnesium, it will be appreciated that various other processes may be used to deposit these materials. For example, deposition may be conducted using other PVD processes (including sputtering), CVD processes (including plasma enhanced chemical vapor deposition (PECVD)), or other suitable processes for depositing such materials. In some embodiments, magnesium is deposited by heating a magnesium source material using a resistive heater. In other embodiments, a magnesium source material may be loaded in a heated crucible, a heated boat, a Knudsen cell (e.g., an effusion evaporator source), or any other type of evaporation source.

A deposition source material used to deposit a conductive coating may be a mixture or a compound, and, in some embodiments, at least one component of the mixture or compound is not deposited on a substrate during deposition (or is deposited in a relatively small amount compared to, for example, magnesium). In some embodiments, the source material may be a copper-magnesium (Cu—Mg) mixture or a Cu—Mg compound. In some embodiments, the source material for a magnesium deposition source includes magnesium and a material with a lower vapor pressure than magnesium, such as, for example, Cu. In other embodiments, the source material for a magnesium deposition source is substantially pure magnesium. Specifically, substantially pure magnesium can exhibit substantially similar properties (e.g., initial sticking probabilities on nucleation inhibiting and promoting coatings) compared to pure magnesium (99.99% and higher purity magnesium). For example, an initial sticking probability of substantially pure magnesium on a nucleation inhibiting coating can be within ±10% or within ±5% of an initial sticking probability of 99.99% purity magnesium on the nucleation inhibiting coating. Purity of magnesium may be about 95% or higher, about 98% or higher, about 99% or higher, or about 99.9% or higher. Deposition source materials used to deposit a conductive coating may include other metals in place of, or in combination with, magnesium. For example, a source material may include high vapor pressure materials, such as ytterbium (Yb), cadmium (Cd), zinc (Zn), or any combination thereof.

Furthermore, it will be appreciated that the processes of various embodiments may be performed on surfaces of other various organic or inorganic materials used as an electron injection layer, an electron transport layer, an electroluminescent layer, and/or a pixel definition layer (PDL) of an organic opto-electronic device. Examples of such materials include organic molecules as well as organic polymers such as those described in PCT Publication No. WO 2012/016074. It will also be understood by persons skilled in the art that organic materials doped with various elements and/or inorganic compounds may still be considered to be an organic material. It will further be appreciated by those skilled in the art that various organic materials may be used, and the processes described herein are generally applicable to an entire range of such organic materials.

It will also be appreciated that an inorganic substrate or surface can refer to a substrate or surface primarily including an inorganic material. For greater clarity, an inorganic material will generally be understood to be any material that is not considered to be an organic material. Examples of inorganic materials include metals, glasses, and minerals. Specifically, a conductive coating including magnesium may be deposited using a process according to the present disclosure on surfaces of lithium fluoride (LiF), glass and silicon (Si). Other surfaces on which the processes according to the present disclosure may be applied include those of silicon or silicone-based polymers, inorganic semiconductor materials, electron injection materials, salts, metals, and metal oxides.

It will be appreciated that a substrate may include a semiconductor material, and, accordingly, a surface of such a substrate may be a semiconductor surface. A semiconductor material may be described as a material which generally exhibits a band gap. For example, such a band gap may be formed between a highest occupied molecular orbital (HOMO) and a lowest unoccupied molecular orbital (LUMO). Semiconductor materials thus generally possess electrical conductivity that is less than that of a conductive material (e.g., a metal) but greater than that of an insulating material (e.g., a glass). It will be understood that a semiconductor material may be an organic semiconductor material or an inorganic semiconductor material.

FIG. 17 shows a patterned cathode 1710 according to one embodiment. The cathode 1710 is illustrated as a single monolithic or continuous structure including a plurality of substantially straight conductor segments, which are spaced apart and arranged substantially parallel with respect to one another. Each conductor segment is connected at both of its ends to end conductor segments, which are arranged substantially perpendicular to the plurality of substantially straight conductor segments. The cathode 1710 can be formed in accordance with the deposition processes described above.

FIG. 17B shows a patterned cathode 1712 according to another embodiment, in which the cathode 1712 includes a plurality of spaced apart and elongated conductive strips. For example, the cathode 1712 may be used in a passive matrix OLED device (PMOLED) 1715. In the PMOLED device 1715, emissive regions or pixels are generally formed at regions where counter-electrodes overlap. Accordingly, in the embodiment of FIG. 17B, emissive regions or pixels 1751 are formed at overlapping regions of the cathode 1712 and an anode 1741, which includes a plurality of spaced apart and elongated conductive strips. Non-emissive regions 1755 are formed at regions where the cathode 1712 and the anode 1741 do not overlap. Generally, the strips of the cathode 1712 and the strips of the anode 1741 are oriented substantially perpendicular to each other in the PMOLED device 1715 as illustrated. The cathode 1712 and the anode 1741 may be connected to a power source and associated driving circuitry for supplying current to the respective electrodes.

FIG. 17C illustrates a cross-sectional view taken along line A-A in FIG. 17B. In FIG. 17C, a base substrate 1702 is provided, which may be, for example, a transparent substrate. The anode 1741 is provided over the base substrate 1702 in the form of strips as illustrated in FIG. 17B. One or more organic layers 1761 are deposited over the anode 1741. For example, the organic layers 1761 may be provided as a common layer across the entire device, and may include any number of layers of organic and/or inorganic materials described herein, such as hole injection and transport layers, an electroluminescence layer, and electron transport and injection layers. Certain regions of a top surface of the organic layers 1761 are illustrated as being covered by a nucleation inhibition coating 1771, which is used to selectively pattern the cathode 1712 in accordance with the deposition processes described above. The cathode 1712 and the anode 1741 may be connected to their respective drive circuitry (not shown), which controls emission of light from the pixels 1751.

While thicknesses of the nucleation inhibiting coating 1771 and the cathode 1712 may be varied depending on the desired application and performance, at least in some embodiments, the thickness of the nucleation inhibiting coating 1771 may be comparable to, or substantially less than, the thickness of the cathode 1712 as illustrated in FIG. 17C. The use of a relatively thin nucleation inhibiting coating to achieve patterning of a cathode may be particularly advantageous for flexible PMOLED devices, since it can provide a relatively planar surface onto which a barrier coating may be applied.

FIG. 17D illustrates the PMOLED device 1715 of FIG. 17C with a barrier coating 1775 applied over the cathode 1712 and the nucleation inhibiting coating 1771. As will be appreciated, the barrier coating 1775 is generally provided to inhibit the various device layers, including organic layers and the cathode 1712 which may be prone to oxidation, from being exposed to moisture and ambient air. For example, the barrier coating 1775 may be a thin film encapsulation formed by printing, CVD, sputtering, atomic-layer deposition (ALD), any combinations of the foregoing, or by any other suitable methods. The barrier coating 1775 may also be provided by laminating a pre-formed barrier film onto the device 1715 using an adhesive (not shown). For example, the barrier coating 1775 may be a multi-layer coating comprising organic materials, inorganic materials, or combination of both. The barrier coating 1775 may further comprise a getter material and/or a desiccant.

For comparative purposes, an example of a comparative PMOLED device 1719 is illustrated in FIG. 17E. In the comparative example of FIG. 17E, a plurality of pixel definition structures 1783 are provided in non-emissive regions of the device 1719, such that when a conductive material is deposited using an open mask or a mask-free deposition process, the conductive material is deposited on both emissive regions located between neighboring pixel definition structures 1783 to form the cathode 1712, as well as on top of the pixel definition structures 1783 to form conductive strips 1718. However, in order to ensure that each segment of the cathode 1712 is electrically isolated from the conductive strips 1718, a thickness or height of the pixel definition structures 1783 are formed to be greater than a thickness of the cathode 1712. The pixel definition structures 1783 may also have an undercut profile to further decrease the likelihood of the cathode 1712 coming in electrical contact with the conductive strips 1718. The barrier coating 1775 is provided to cover the PMOLED device 1719 including the cathode 1712, the pixel definition structures 1783, and the conductive strips 1718.

In the comparative PMOLED device 1719 illustrated in FIG. 17E, the surface onto which the barrier coating 1775 is applied is non-uniform due to the presence of the pixel definition structures 1783. This makes the application of the barrier coating 1775 difficult, and even upon the application of the barrier coating 1775, the adhesion of the barrier coating 1775 to the underlying surface may be relatively poor. Poor adhesion increases the likelihood of the barrier coating 1775 peeling off the device 1719, particularly when the device 1719 is bent or flexed. Additionally, there is a relatively high probability of air pockets being trapped between the barrier coating 1775 and the underlying surface during the application procedure due to the non-uniform surface. The presence of air pockets and/or peeling of the barrier coating 1775 can cause or contribute to defects and partial or total device failure, and thus is highly undesirable. These factors are mitigated or reduced in the embodiment of FIG. 17D.

While the patterned cathodes 1710 and 1712 shown in FIGS. 17 and 17B may be used to form a cathode of an OLED device, it is appreciated that a similar pattern may be used to form an auxiliary electrode for an OLED device. Specifically, such an OLED device may be provided with a common cathode, and an auxiliary electrode deposited on top of, or beneath, the common cathode such that the auxiliary electrode is in electrical communication with the common cathode. For example, such an auxiliary electrode may be implemented in an OLED device including a plurality of emissive regions (e.g., an AMOLED device) such that the auxiliary electrode is formed over non-emissive regions, and not over the emissive regions. In another example, an auxiliary electrode may be provided to cover non-emissive regions as well as at least some emissive regions of an OLED device.

FIG. 18A depicts a portion of an OLED device 1800 including a plurality of emissive regions 1810 a-1810 f and a non-emissive region 1820. For example, the OLED device 1800 may be an AMOLED device, and each of the emissive regions 1810 a-1810 f may correspond to a pixel or a subpixel of such a device. For sake of simplicity, FIGS. 18B-18D depict a portion of the OLED device 1800. Specifically, FIGS. 18B-18D show a region surrounding a first emissive region 1810 a and a second emissive region 1810 b, which are two neighboring emissive regions. While not explicitly illustrated, a common cathode may be provided that substantially covers both emissive regions and non-emissive regions of the device 1800.

In FIG. 18B, an auxiliary electrode 1830 according to one embodiment is shown, in which the auxiliary electrode 1830 is disposed between the two neighboring emissive regions 1810 a and 1810 b. The auxiliary electrode 1830 is electrically connected to the common cathode (not shown). Specifically, the auxiliary electrode 1830 is illustrated as having a width (a), which is less than a separation distance (d) between the neighboring emissive regions 1810 a and 1810 b, thus creating a non-emissive gap region on each side of the auxiliary electrode 1830. For example, such an arrangement may be desirable in the device 1800 where the separation distance between the neighboring emissive regions 1810 a and 1810 b are sufficient to accommodate the auxiliary electrode 1830 of sufficient width, since the likelihood of the auxiliary electrode 1830 interfering with an optical output of the device 1800 can be reduced by providing the non-emissive gap regions. Furthermore, such an arrangement may be particularly beneficial in cases where the auxiliary electrode 1830 is relatively thick (e.g., greater than several hundred nanometers or on the order a few microns thick). For example, a ratio of a height or a thickness of the auxiliary electrode 1830 relative to its width (namely, an aspect ratio) may be greater than about 0.05, such as about 0.1 or greater, about 0.2 or greater, about 0.5 or greater, about 0.8 or greater, about 1 or greater, or about 2 or greater. For example, the height or the thickness of the auxiliary electrode 1830 may be greater than about 50 nm, such as about 80 nm or greater, about 100 nm or greater, about 200 nm or greater, about 500 nm or greater, about 700 nm or greater, about 1000 nm or greater, about 1500 nm or greater, about 1700 nm or greater, or about 2000 nm or greater.

In FIG. 18C, an auxiliary electrode 1832 according to another embodiment is shown. The auxiliary electrode 1832 is electrically connected to the common cathode (not shown). As illustrated, the auxiliary electrode 1832 has substantially the same width as the separation distance between the two neighboring emissive regions 1810 a and 1810 b, such that the auxiliary electrode 1832 substantially fully occupies the entire non-emissive region provided between the neighboring emissive regions 1810 a and 1810 b. Such an arrangement may be desirable, for example, in cases where the separation distance between the two neighboring emissive regions 1810 a and 1810 b is relatively small, such as in a high pixel density display device.

In FIG. 18D, an auxiliary electrode 1834 according to yet another embodiment is illustrated. The auxiliary electrode 1834 is electrically connected to the common cathode (not shown). The auxiliary electrode 1834 is illustrated as having a width (a), which is greater than the separation distance (d) between the two neighboring emissive regions 1810 a and 1810 b. Accordingly, a portion of the auxiliary electrode 1834 overlaps a portion of the first emissive region 1810 a and a portion of the second emissive region 1810 b. Such an arrangement may be desirable, for example, in cases where the non-emissive region between the neighboring emissive regions 1810 a and 1810 b is not sufficient to fully accommodate the auxiliary electrode 1834 of the desired width. While the auxiliary electrode 1834 is illustrated in FIG. 18D as overlapping with the first emissive region 1810 a to substantially the same degree as the second emissive region 1810 b, the extent to which the auxiliary electrode 1834 overlaps with an adjacent emissive region may be modulated in other embodiments. For example, in other embodiments, the auxiliary electrode 1834 may overlap to a greater extent with the first emissive region 1810 a than the second emissive region 1810 b and vice versa. Furthermore, a profile of overlap between the auxiliary electrode 1834 and an emissive region can also be varied. For example, an overlapping portion of the auxiliary electrode 1834 may be shaped such that the auxiliary electrode 1834 overlaps with a portion of an emissive region to a greater extent than it does with another portion of the same emissive region to create a non-uniform overlapping region.

In FIG. 19, an OLED device 1900 according to one embodiment is illustrated in which an emissive region 1910 and a non-emissive region 1920 surrounding the emissive region 1910 are provided. A lead 1912 is illustrated as being formed in the non-emissive region 1920 of the device 1900. The lead 1912 is electrically connected to an electrode (not shown) covering the emissive region 1910 of the device 1900. The lead 1912 may provide a contact point for connecting to an external power supply for powering such an electrode. For example, the electrode may be connected to the external power supply via the lead 1912 by a soldering pad provided integral to the lead 1912 (to which an electrical wire may be soldered and connected to the power supply). It will be appreciated that, while not explicitly illustrated, an auxiliary electrode may be present and connected to the electrode covering the emissive region 1910 of the device 1900. Where such an auxiliary electrode is present, the lead 1912 may be directly connected to the auxiliary electrode, the electrode to which the auxiliary electrode is connected, or both.

It will be appreciated that the lead 1912 may be provided on a same plane as the electrode to which it is connected, or it may be provided on a different plane. For example, the lead 1912 may be connected to another layer of the OLED device 1900, such as a backplane through one or more vertical connections (e.g., vias).

FIG. 20 illustrates a portion of an OLED device 2000 according to another embodiment. The OLED device 2000 includes an emissive region 2010 and a non-emissive region 2020. The OLED device 2000 further includes a grid-like auxiliary electrode 2030, which is in electrical communication with an electrode (not shown) of the device 2000. As illustrated in FIG. 20, a first portion of the auxiliary electrode 2030 is disposed within the emissive region 2010, while a second portion of the auxiliary electrode 2030 is disposed outside of the emissive region 2010 and within the non-emissive region 2020 of the device 2000. Such an arrangement of the auxiliary electrode 2030 may allow a sheet resistance of the electrode to be reduced while keeping the auxiliary electrode 2030 from significantly interfering with an optical output of the device 2000.

In some applications, it may be desirable to form a regular repeating pattern of an auxiliary electrode over an entire device area or a portion thereof. FIGS. 21A-21D illustrate various embodiments of repeating units of an auxiliary electrode that may be used. Specifically, in FIG. 21A, an auxiliary electrode 2110 encompasses four regions 2120 which are not covered by the auxiliary electrode 2110. The auxiliary electrode 2110 is formed such that the regions 2120 are arranged in a T-shape. For example, each of the regions 2120 may substantially correspond to an emissive region of an OLED device including a plurality of emissive regions. Accordingly, it will be appreciated that other layers or coatings, such as a common cathode, may be present in the regions 2120. In FIG. 21B, an auxiliary electrode 2112 is formed in an inverted T-shape and encompasses four uncovered regions 2122. In FIG. 21C, an auxiliary electrode 2114 is formed to encompass four uncovered regions 2124, and, similarly in FIG. 21D, an auxiliary electrode 2116 is formed to encompass four uncovered regions 2126.

Potential advantages of using repeating units of an auxiliary electrode, such as those illustrated in FIGS. 21A-21D, include ease of patterning in fabricating devices. For example, a mask used in patterning a nucleation promoting or nucleation inhibiting coating during the formation of the auxiliary electrode may be used repeatedly to pattern different portions of a device surface, thus obviating the need for more complex and/or larger masks.

FIG. 22 depicts a portion of an OLED device 2200 according to one embodiment, in which the device 2200 includes a plurality of repeating auxiliary electrode units 2230 a-d formed thereon. Specifically, each auxiliary electrode unit 2230 a-d is L-shaped and encompasses three distinct emitting regions 2210. For example, each emitting region 2210 may correspond to a pixel or a sub-pixel of the device 2200. As illustrated, neighboring auxiliary electrode units may interlock with one another. For example, a first auxiliary electrode unit 2230 a is formed to be in an interlocking relationship with a second auxiliary electrode unit 2230 b, and, similarly, a third auxiliary electrode unit 2230 c is interlocked with a fourth auxiliary electrode unit 2230 d. The auxiliary electrode units 2230 a-d are formed on a non-emissive region 2220. It will be appreciated that the auxiliary electrode units 2230 a-d may be formed such that they are in direct electrical communication with one another. For example, the repeating auxiliary electrode units 2230 a-d may be formed integrally during fabrication. Alternatively, the auxiliary electrode units 2230 a-d may be formed such that they are electrically connected via a common electrode.

FIG. 23 illustrates a portion of an OLED device 2300 according to another embodiment. In the embodiment of FIG. 23, each auxiliary electrode unit 2330 a, 2330 b is formed to encompass five distinct emissive regions 2310. The auxiliary electrode units 2330 a and 2330 b are formed on a non-emissive region 2320 of the device 2300. As illustrated, a first auxiliary electrode unit 2330 a is positioned adjacent to, but not in an interlocking relationship with, a second auxiliary electrode unit 2330 b.

In another embodiment illustrated in FIG. 24, similar auxiliary electrode units as those illustrated in FIG. 23 are provided. However, in FIG. 24, auxiliary electrode units 2430 a-d are arranged in an interlocking relationship with one another. Similarly to the embodiment of FIG. 23, each auxiliary electrode unit 2430 a-d encompasses five distinct emissive regions 2410, and are formed on a non-emissive region 2420 of a device 2400.

While various embodiments in which each auxiliary electrode unit encompasses 3, 4, or 5 emissive regions have been described and illustrated, it will be appreciated that each auxiliary electrode unit may encompass any number of emissive regions, including 1, 2, 3, 4, 5, 6, or more emissive regions.

FIG. 25 illustrates an embodiment in which an auxiliary electrode 2530 is formed as a grid over an OLED device 2500. As illustrated, the auxiliary electrode is 2530 provided over a non-emissive region 2520 of the device 2500, such that it does not substantially cover any portion of emissive regions 2510.

FIG. 26 illustrates an embodiment in which auxiliary electrode units 2630 are formed as series of elongated structures over an OLED device 2600. As illustrated, the auxiliary electrode units 2630 are provided over a non-emissive region 2620 of the device 2600, such that it does not substantially cover any portion of emissive regions 2610. The auxiliary electrode units 2610 are spaced apart and not physically connected to one another, but rather are electrically connected via a common electrode (not shown). As would be appreciated, the auxiliary electrode units 2610 which are not directly interconnected to one another may still provide substantial advantage by lowering an overall sheet resistance of the connected common electrode.

FIG. 27 illustrates an embodiment in which auxiliary electrode units 2730 are formed in a “stair case” pattern over an OLED device 2700. As illustrated, the auxiliary electrode units 2730 are provided over a non-emissive region 2720 of the device 2700, such that it does not substantially cover any portion of emissive regions 2710.

FIGS. 28A-28J illustrate various embodiments in which an auxiliary electrode is provided between neighboring subpixels.

In FIG. 28A, auxiliary electrode units 2830 are provided as elongated strips between neighboring columns of subpixels 2812. Specifically in the embodiment of FIG. 28A, a first subpixel 2812 a, a second subpixel 2812 b, and a third subpixel 2812 c collectively form a first pixel 2810 a. For example, the first pixel 2810 a may be an RGB pixel, in which case each subpixel 2812 a-c would correspond to a red, a green, or a blue subpixel. Pixels 2810 may be arranged such that a same subpixel pattern (e.g., red, green, blue) is repeated across a display device. Specifically, a subpixel arrangement of a second pixel 2810 b and a third pixel 2810 c may be identical to that of the first pixel 2810 a. In such an arrangement, all of the subpixels 2812 in each column of subpixels 2812 (e.g., subpixels arranged linearly along a first axis labelled Y) may be identical in color, and the auxiliary electrode unit 2830 extending substantially parallel to the first axis Y may be provided between neighboring columns of subpixels 2812 as illustrated in FIG. 28A.

For sake of simplicity, FIG. 28B-28J are illustrated using identical pixel and subpixel arrangements as that described in reference to FIG. 28A above.

In FIG. 28B, auxiliary electrode units 2830 are illustrated as being provided between neighboring columns of pixels 2810. Specifically, the auxiliary electrode unit 2830 that extends substantially parallel to the first axis Y is provided between the first pixel 2810 a and the second pixel 2810 b, which are aligned in the direction of a second axis X with respect to each other. However, no auxiliary electrode unit 2830 is provided between the first pixel 2810 a and the third pixel 2810 c, which are aligned in the direction of the first axis Y with respect to each other. The first axis Y and the second axis X are perpendicular to one another as illustrated in the figures. It will be appreciated that while the auxiliary electrode units 2830 are illustrated in FIG. 28B as extending along the first axis Y, the auxiliary electrode units 2830 may extend along the second axis X in another embodiment.

FIG. 28C illustrates an embodiment in which an auxiliary electrode 2830 is provided as a grid across a display device between neighboring subpixels 2812. Specifically, the auxiliary electrode 2830 is provided between each pair of neighboring subpixels 2812 a-2812 c. Accordingly, the auxiliary electrode 2830 includes segments, which extend substantially parallel to the first axis Y and the second axis X to form a mesh or a grid between the subpixels 2812 a-2812 c.

In another embodiment illustrated in FIG. 28D, an auxiliary electrode 2830 is provided between neighboring pixels 2810. Specifically, the auxiliary electrode 2830 is provided between the first pixel 2810 a and the second pixel 2810 b which are aligned along the second axis X with respect to each other, as well as between the first pixel 2810 a and the third pixel 2810 c which are aligned along the first axis Y with respect to each other. Accordingly, the auxiliary electrode 2830 forms a mesh or a grid between the pixels 2810 a-c.

In FIG. 28E, a yet another embodiment is illustrated in which discrete auxiliary electrode units 2830 are provided between neighboring subpixels 2812. Specifically, the auxiliary electrode units 2830 are oriented substantially parallel to the first axis Y and are provided between the neighboring subpixels 2812 a-c.

In FIG. 28F, an embodiment is illustrated in which discrete auxiliary electrode units 2830 are provided between neighboring pixels 2810. Specifically, the auxiliary electrode unit 2830 is oriented substantially parallel to the first axis Y and is provided between the first pixel 2810 a and the second pixel 2810 b, which are arranged adjacent to each other along the second axis X.

In FIG. 28G, discrete auxiliary electrode units 2830 are provided between neighboring subpixels 2812 to create a grid or a mesh across a display device. As illustrated, the elongated auxiliary electrode units 2830 which extend substantially parallel to the first axis Y are disposed between neighboring subpixels 2812 aligned along the second axis X. Similarly, the elongated auxiliary electrode units 2830 extending substantially parallel to the second axis X are disposed between neighboring subpixels 2812 aligned along the first axis Y.

In FIG. 28H, discrete auxiliary electrode units 2830 are provided between neighboring pixels 2810 to create a grid or a mesh across a display device. As illustrated, the elongated auxiliary electrode unit 2830 which extends substantially parallel to the first axis Y is disposed between neighboring pixels 2810 a and 2810 b aligned along the second axis X. Similarly, the elongated auxiliary electrode unit 2830 extending substantially parallel to the second axis X is disposed between neighboring pixels 2810 a and 2810 c aligned along the first axis Y.

FIG. 28I illustrates another embodiment in which discrete auxiliary electrode units 2830 are provided between neighboring subpixels 2812 to form a grid or a mesh across a display device. The auxiliary electrode units 2830 each comprises a first segment extending substantially parallel to the first axis Y and a second segment extending substantially parallel to the second axis X. The first axis Y and the second axis X are perpendicular to one another. In FIG. 28I, the first segment and the second segment are connected end-to-end to form an inverted L-shape.

FIG. 28J illustrates another embodiment in which discrete auxiliary electrode units 2830 are provided between neighboring subpixels 2812 to form a grid or a mesh across a display device. The auxiliary electrode units 2830 each comprises a first segment extending substantially parallel to the first axis Y and a second segment extending substantially parallel to the second axis X. The first axis Y and the second axis X are perpendicular to one another. In FIG. 28J, the first segment and the second segment are connected near a mid-point of the first and the second segments to form a cross shape.

While auxiliary electrode units have been illustrated in certain embodiments as not being physically connected to one another, they may be nevertheless in electrical communication with one another via a common electrode. For example, providing discrete auxiliary electrode units, which are indirectly connected to one another via the common electrode, may still substantially lower a sheet resistance and thus increase an efficiency of an OLED device without substantially interfering with optical characteristics of the device.

Auxiliary electrodes may also be used in display devices with other pixel or sub-pixel arrangements. For example, auxiliary electrodes may be provided on a display device in which a diamond pixel arrangement is used. Examples of such pixel arrangements are illustrated in FIGS. 29-33.

FIG. 29 is a schematic illustration of an OLED device 2900 having a diamond pixel arrangement according to one embodiment. The OLED device 2900 includes a plurality of pixel definition layers (PDLs) 2930 and emissive regions 2912 (sub-pixels) disposed between neighboring PDLs 2930. The emissive regions 2912 include those corresponding to first sub-pixels 2912 a, which may, for example, correspond to green sub-pixels, second sub-pixels 2912 b, which may, for example, correspond to blue sub-pixels, and third sub-pixels 2912 c, which may, for example, correspond to red sub-pixels.

FIG. 30 is a schematic illustration of the OLED device 2900 taken along line A-A shown in FIG. 29. As more clearly illustrated in FIG. 30, the device 2900 includes a substrate 2903 and a plurality of anode units 2921 formed on a surface of the base substrate 2903. The substrate 2903 may further include a plurality of transistors and a base substrate, which have been omitted from the figure for sake of simplicity. An organic layer 2915 is provided on top of each anode unit 2921 in a region between neighboring PDLs 2930, and a common cathode 2942 is provided over the organic layer 2915 and the PDLs 2930 to form the first sub-pixels 2912 a. The organic layer 2915 may include a plurality of organic and/or inorganic layers. For example, such layers may include a hole transport layer, a hole injection layer, an electroluminescence layer, an electron injection layer, and/or an electron transport layer. A nucleation inhibiting coating 2945 is provided over regions of the common cathode 2942 corresponding to the first sub-pixels 2912 a to allow selective deposition of an auxiliary electrode 2951 over uncovered regions of the common cathode 2942 corresponding to substantially planar regions of the PDLs 2930. The nucleation inhibiting coating 2945 may also act as an index-matching coating. A thin film encapsulation layer 2961 may optionally be provided to encapsulate the device 2900.

FIG. 31 shows a schematic illustration of the OLED device 2900 taken along line B-B indicated in FIG. 29. The device 2900 includes the plurality of anode units 2921 formed on the surface of the substrate 2903, and an organic layer 2916 or 2917 provided on top of each anode unit 2921 in a region between neighboring PDLs 2930. The common cathode 2942 is provided over the organic layers 2916 and 2917 and the PDLs 2930 to form the second sub-pixel 2912 b and the third sub-pixel 2912 c, respectively. The nucleation inhibiting coating 2945 is provided over regions of the common cathode 2942 corresponding to the sub-pixels 2912 b and 2912 c to allow selective deposition of the auxiliary electrode 2951 over uncovered regions of the common cathode 2942 corresponding to the substantially planar regions of the PDLs 2930. The nucleation inhibiting coating 2945 may also act as an index-matching coating. The thin film encapsulation layer 2961 may optionally be provided to encapsulate the device 2900.

FIG. 32 is a schematic illustration of an OLED device 3200 with a pixel arrangement according to another embodiment. Specifically, the device 3200 includes a plurality of PDLs 3230 separating emissive regions 3212 (sub-pixels). For example, first sub-pixels 3212 a may correspond to green sub-pixels, second sub-pixels 3212 b may correspond to blue sub-pixels, and third sub-pixels 3212 c may correspond to red sub-pixels. FIG. 33 is an image of an OLED device with the pixel arrangement according to the embodiment of FIG. 32. Although not shown, the device 3200 may further include an auxiliary electrode provided over non-emissive regions of the device 3200. For example, the auxiliary electrode may be disposed over regions of a common cathode corresponding to substantially planar portions of the PDLs 3230.

In another aspect according to some embodiments, a device is provided. In some embodiments, the device is an opto-electronic device. In some embodiments, the device is another electronic device or other product. In some embodiments, the device includes a substrate, a nucleation inhibiting coating, and a conductive coating. The nucleation inhibiting coating covers a first region of the substrate. The conductive coating covers a second region of the substrate, and partially overlaps the nucleation inhibiting coating such that at least a portion of the nucleation inhibiting coating is exposed from, or is substantially free of or is substantially uncovered by, the conductive coating. In some embodiments, the conductive coating includes a first portion and a second portion, the first portion of the conductive coating covers the second region of the substrate, and the second portion of the conductive coating overlaps a portion of the nucleation inhibiting coating. In some embodiments, the second portion of the conductive coating is spaced from the nucleation inhibiting coating by a gap. In some embodiments, the nucleation inhibiting coating includes an organic material. In some embodiments, the first portion of the conductive coating and the second portion of the conductive coating are integrally formed with one another.

In another aspect according to some embodiments, a device is provided. In some embodiments, the device is an opto-electronic device. In some embodiments, the device is another electronic device or other product. In some embodiments, the device includes a substrate and a conductive coating. The substrate includes a first region and a second region. The conductive coating covers the second region of the substrate, and partially overlaps the first region of the substrate such that at least a portion of the first region of the substrate is exposed from, or is substantially free of or is substantially uncovered by, the conductive coating. In some embodiments, the conductive coating includes a first portion and a second portion, the first portion of the conductive coating covers the second region of the substrate, and the second portion of the conductive coating overlaps a portion of the first region of the substrate. In some embodiments, the second portion of the conductive coating is spaced from the first region of the substrate by a gap. In some embodiments, the first portion of the conductive coating and the second portion of the conductive coating are integrally formed with one another.

FIG. 34 illustrates a portion of a device according to one embodiment. The device includes a substrate 3410 having a surface 3417. A nucleation inhibiting coating 3420 covers a first region 3415 of the surface 3417 of the substrate 3410, and a conductive coating 3430 covers a second region 3412 of the surface 3417 of the substrate 3410. As illustrated in FIG. 34, the first region 3415 and the second region 3412 are distinct and non-overlapping regions of the surface 3417 of the substrate 3410. The conductive coating 3430 includes a first portion 3432 and a second portion 3434. As illustrated in the figure, the first portion 3432 of the conductive coating 3430 covers the second region 3412 of the substrate 3410, and the second portion 3434 of the conductive coating 3430 partially overlaps a portion of the nucleation inhibiting coating 3420. Specifically, the second portion 3434 is illustrated as overlapping the portion of the nucleation inhibiting coating 3420 in a direction that is perpendicular (or normal) to the underlying substrate surface 3417.

Particularly in the case where the nucleation inhibiting coating 3420 is formed such that its surface 3422 exhibits a relatively low initial sticking probability against a material used to form the conductive coating 3430, there is a gap 3441 formed between the overlapping, second portion 3434 of the conductive coating 3430 and the surface 3422 of the nucleation inhibiting coating 3420. Accordingly, the second portion 3434 of the conductive coating 3430 is not in direct physical contact with the nucleation inhibiting coating 3420, but is spaced from the nucleation inhibiting coating 3420 by the gap 3441 along the direction perpendicular to the surface 3417 of the substrate 3410 as indicated by arrow 3490. Nevertheless, the first portion 3432 of the conductive coating 3430 may be in direct physical contact with the nucleation inhibiting coating 3420 at an interface or a boundary between the first region 3415 and the second region 3412 of the substrate 3410.

In some embodiments, the overlapping, second portion 3434 of the conductive coating 3430 may laterally extend over the nucleation inhibiting coating 3420 by a comparable extent as a thickness of the conductive coating 3430. For example, in reference to FIG. 34, a width w₂ (or a dimension along a direction parallel to the surface 3417 of the substrate 3410) of the second portion 3434 may be comparable to a thickness t₁ (or a dimension along a direction perpendicular to the surface 3417 of the substrate 3410) of the first portion 3432 of the conductive coating 3430. For example, a ratio of w₂:t₁ may be in a range of about 1:1 to about 1:3, about 1:1 to about 1:1.5, or about 1:1 to about 1:2. While the thickness t₁ would generally be relatively uniform across the conductive coating 3430, the extent to which the second portion 3434 overlaps with the nucleation inhibiting coating 3420 (namely, w₂) may vary to some extent across different portions of the surface 3417.

In another embodiment illustrated in FIG. 35, the conductive coating 3430 further includes a third portion 3436 disposed between the second portion 3434 and the nucleation inhibiting coating 3420. As illustrated, the second portion 3434 of the conductive coating 3430 laterally extends over and is spaced from the third portion 3436 of the conductive coating 3430, and the third portion 3436 may be in direct physical contact with the surface 3422 of the nucleation inhibiting coating 3420. A thickness t₃ of the third portion 3436 may be less, and, in some cases, substantially less than the thickness t₁ of the first portion 3432 of the conductive coating 3430. Furthermore, at least in some embodiments, a width w₃ of the third portion 3436 may be greater than the width w₂ of the second portion 3434. Accordingly, the third portion 3436 may extend laterally to overlap with the nucleation inhibiting coating 3420 to a greater extent than the second portion 3434. For example, a ratio of w₃:t₁ may be in a range of about 1:2 to about 3:1 or about 1:1.2 to about 2.5:1. While the thickness t₁ would generally be relatively uniform across the conductive coating 3430, the extent to which the third portion 3436 overlaps with the nucleation inhibiting coating 3420 (namely, w₃) may vary to some extent across different portions of the surface 3417. The thickness t₃ of the third portion 3436 may be no greater than or less than about 5% of the thickness t₁ of the first portion 3432. For example, t₃ may be no greater than or less than about 4%, no greater than or less than about 3%, no greater than or less than about 2%, no greater than or less than about 1%, or no greater than or less than about 0.5% of t₁. Instead of, or in addition to, the third portion 3436 being formed as a thin film as shown in FIG. 35, the material of the conductive coating 3430 may form as islands or disconnected clusters on a portion of the nucleation inhibiting coating 3420. For example, such islands or disconnected clusters may include features which are physically separated from one another, such that the islands or clusters are not formed as a continuous layer.

In yet another embodiment illustrated in FIG. 36, a nucleation promoting coating 3451 is disposed between the substrate 3410 and the conductive coating 3430. Specifically, the nucleation promoting coating 3451 is disposed between the first portion 3432 of the conducting coating 3430 and the second region 3412 of the substrate 3410. The nucleation promoting coating 3451 is illustrated as being disposed on the second region 3412 of the substrate 3410, and not on the first region 3415 where the nucleation inhibiting coating 3420 is deposited. The nucleation promoting coating 3451 may be formed such that, at an interface or a boundary between the nucleation promoting coating 3451 and the conductive coating 3430, a surface of the nucleation promoting coating 3451 exhibits a relatively high initial sticking probability for the material of the conductive coating 3430. As such, the presence of the nucleation promoting coating 3451 may promote the formation and growth of the conductive coating 3430 during deposition. Various features of the conducting coating 3430 (including the dimensions of the first portion 3432 and the second portion 3434) and other coatings of FIG. 36 can be similar to those described above for FIGS. 34-35 and are not repeated for brevity.

In yet another embodiment illustrated in FIG. 37, the nucleation promoting coating 3451 is disposed on both the first region 3415 and the second region 3412 of the substrate 3410, and the nucleation inhibiting coating 3420 covers a portion of the nucleation promoting coating 3451 disposed on the first region 3415. Another portion of the nucleation promoting coating 3451 is exposed from, or is substantially free of or is substantially uncovered by, the nucleation inhibiting coating 3420, and the conductive coating 3430 covers the exposed portion of the nucleation promoting coating 3451. Various features of the conducting coating 3430 and other coatings of FIG. 37 can be similar to those described above for FIGS. 34-35 and are not repeated for brevity.

FIG. 38 illustrates a yet another embodiment in which the conductive coating 3430 partially overlaps a portion of the nucleation inhibiting coating 3420 in a third region 3419 of the substrate 3410. Specifically, in addition to the first portion 3432 and the second portion 3434, the conductive coating 3430 further includes a third portion 3480. As illustrated in the figure, the third portion 3480 of the conductive coating 3430 is disposed between the first portion 3432 and the second portion 3434 of the conductive coating 3430, and the third portion 3480 may be in direct physical contact with the surface 3422 of the nucleation inhibiting coating 3420. In this regard, the overlap in the third region 3419 may be formed as a result of lateral growth of the conductive coating 3430 during an open mask or mask-free deposition process. More specifically, while the surface 3422 of the nucleation inhibiting coating 3420 may exhibit a relatively low initial sticking probability for the material of the conductive coating 3430 and thus the probability of the material nucleating on the surface 3422 is low, as the conductive coating 3430 grows in thickness, the coating 3430 may also grow laterally and may cover a portion of the nucleation inhibiting coating 3420 as illustrated in FIG. 38.

While details regarding certain features of the device and the conductive coating 3430 have been omitted in the above description for the embodiments of FIGS. 36-38, it will be appreciated that descriptions of various features including the gap 3441, the second portion 3434, and the third portion 3436 of the conductive coating 3430 described in relation to FIG. 34 and FIG. 35 would similarly apply to such embodiments.

It will be appreciated that, while not explicitly illustrated, a material used to form the nucleation inhibiting coating 3420 may also be present to some extent at an interface between the conductive coating 3430 and an underlying surface (e.g., a surface of the nucleation promoting layer 3451 or the substrate 3410). Such material may be deposited as a result of a shadowing effect, in which a deposited pattern is not identical to a pattern of a mask and may result in some evaporated material being deposited on a masked portion of a target surface. For example, such material may form as islands or disconnected clusters, or as a thin film having a thickness that is substantially less than an average thickness of the nucleation inhibiting coating 3420.

In some embodiments, the nucleation inhibiting coating 3420 may be removed subsequent to deposition of the conductive coating 3430, such that at least a portion of an underlying surface covered by the nucleation inhibiting coating 3420 in the embodiments of FIGS. 34-38 becomes exposed. For example, the nucleation inhibiting coating 3420 may be selectively removed by etching or dissolving the nucleation inhibiting coating 3420, or using plasma or solvent processing techniques without substantially affecting or eroding the conductive coating 3430.

A device of some embodiments may be an electronic device, and, more specifically, an opto-electronic device. An opto-electronic device generally encompasses any device that converts electrical signals into photons or vice versa. As such, an organic opto-electronic device can encompass any opto-electronic device where one or more active layers of the device are formed primarily of an organic material, and, more specifically, an organic semiconductor material. Examples of organic opto-electronic devices include, but are not limited to, OLED devices and OPV devices.

It will also be appreciated that organic opto-electronic devices may be formed on various types of base substrates. For example, a base substrate may be a flexible or rigid substrate. The base substrate may include, for example, silicon, glass, metal, polymer (e.g., polyimide), sapphire, or other materials suitable for use as the base substrate.

It will also be appreciated that various components of a device may be deposited using a wide variety of techniques, including vapor deposition, spin-coating, line coating, printing, and various other deposition techniques.

In some embodiments, an organic opto-electronic device is an OLED device, wherein an organic semiconductor layer includes an electroluminescent layer. In some embodiments, the organic semiconductor layer may include additional layers, such as an electron injection layer, an electron transport layer, a hole transport layer, and/or a hole injection layer. For example, the OLED device may be an AMOLED device, PMOLED device, or an OLED lighting panel or module. Furthermore, the opto-electronic device may be a part of an electronic device. For example, the opto-electronic device may be an OLED display module of a computing device, such as a smartphone, a tablet, a laptop, or other electronic device such as a monitor or a television set.

FIGS. 39-41 illustrate various embodiments of an active matrix OLED (AMOLED) display device. For the sake of simplicity, various details and characteristics of a conductive coating at or near an interface between the conductive coating and a nucleation inhibiting coating described above in reference to FIGS. 34-38 have been omitted. However, it will be appreciated that the features described in reference to FIGS. 34-38 may also be applicable to the embodiments of FIGS. 39-41.

FIG. 39 is a schematic diagram illustrating a structure of an AMOLED device 3802 according to one embodiment.

The device 3802 includes a base substrate 3810, and a buffer layer 3812 deposited over a surface of the base substrate 3810. A thin-film transistor (TFT) 3804 is then formed over the buffer layer 3812. Specifically, a semiconductor active area 3814 is formed over a portion of the buffer layer 3812, and a gate insulating layer 3816 is deposited to substantially cover the semiconductor active area 3814. Next, a gate electrode 3818 is formed on top of the gate insulating layer 3816, and an interlayer insulating layer 3820 is deposited. A source electrode 3824 and a drain electrode 3822 are formed such that they extend through openings formed through the interlayer insulating layer 3820 and the gate insulating layer 3816 to be in contact with the semiconductor active layer 3814. An insulating layer 3842 is then formed over the TFT 3804. A first electrode 3844 is then formed over a portion of the insulating layer 3842. As illustrated in FIG. 39, the first electrode 3844 extends through an opening of the insulating layer 3842 such that it is in electrical communication with the drain electrode 3822. Pixel definition layers (PDLs) 3846 are then formed to cover at least a portion of the first electrode 3844, including its outer edges. For example, the PDLs 3846 may include an insulating organic or inorganic material. An organic layer 3848 is then deposited over the first electrode 3844, particularly in regions between neighboring PDLs 3846. A second electrode 3850 is deposited to substantially cover both the organic layer 3848 and the PDLs 3846. A surface of the second electrode 3850 is then substantially covered with a nucleation promoting coating 3852. For example, the nucleation promoting coating 3852 may be deposited using an open mask or a mask-free deposition technique. A nucleation inhibiting coating 3854 is selectively deposited over a portion of the nucleation promoting coating 3852. For example, the nucleation inhibiting coating 3854 may be selectively deposited using a shadow mask. Accordingly, an auxiliary electrode 3856 is selectively deposited over an exposed surface of the nucleation promoting coating 3852 using an open mask or a mask-free deposition process. For further specificity, by conducting thermal deposition of the auxiliary electrode 3856 (e.g., including magnesium) using an open mask or with a mask, the auxiliary electrode 3856 is selectively deposited over the exposed surface of the nucleation promoting coating 3852, while leaving a surface of the nucleation inhibiting coating 3854 substantially free of a material of the auxiliary electrode 3856.

FIG. 40 illustrates a structure of an AMOLED device 3902 according to another embodiment in which a nucleation promoting coating has been omitted. For example, the nucleation promoting coating may be omitted in cases where a surface on which an auxiliary electrode is deposited has a relatively high initial sticking probability for a material of the auxiliary electrode. In other words, for surfaces with a relatively high initial sticking probability, the nucleation promoting coating may be omitted, and a conductive coating may still be deposited thereon. For sake of simplicity, certain details of a backplane including a TFT is omitted in describing the following embodiments.

In FIG. 40, an organic layer 3948 is deposited between a first electrode 3944 and a second electrode 3950. The organic layer 3948 may partially overlap with portions of PDLs 3946. A nucleation inhibiting coating 3954 is deposited over a portion (e.g., corresponding to an emissive region) of the second electrode 3950, thereby providing a surface with a relatively low initial sticking probability (e.g., a relatively low desorption energy) for a material used to form an auxiliary electrode 3956. Accordingly, the auxiliary electrode 3956 is selectively deposited over a portion of the second electrode 3950 that is exposed from the nucleation inhibiting coating 3954. As would be understood, the auxiliary electrode 3956 is in electrical communication with the underlying second electrode 3950 so as to reduce a sheet resistance of the second electrode 3950. For example, the second electrode 3950 and the auxiliary electrode 3956 may include substantially the same material to ensure a high initial sticking probability for the material of the auxiliary electrode 3956. Specifically, the second electrode 3950 may include substantially pure magnesium (Mg) or an alloy of magnesium and another metal, such as silver (Ag). For Mg:Ag alloy, an alloy composition may range from about 1:9 to about 9:1 by volume. The auxiliary electrode 3956 may include substantially pure magnesium.

FIG. 41 illustrates a structure of an AMOLED device 4002 according to yet another embodiment. In the illustrated embodiment, an organic layer 4048 is deposited between a first electrode 4044 and a second electrode 4050 such that it partially overlaps with portions of PDLs 4046. A nucleation inhibiting coating 4054 is deposited so as to substantially cover a surface of the second electrode 4050, and a nucleation promoting coating 4052 is selectively deposited on a portion of the nucleation inhibiting coating 4054. An auxiliary electrode 4056 is then formed over the nucleation promoting coating 4052. Optionally, a capping layer 4058 may be deposited to cover exposed surfaces of the nucleation inhibiting coating 4054 and the auxiliary electrode 4056.

While the auxiliary electrode 3856 or 4056 is illustrated as not being in direct physical contact with the second electrode 3850 or 4050 in the embodiments of FIGS. 39 and 41, it will be understood that the auxiliary electrode 3856 or 4056 and the second electrode 3850 or 4050 may nevertheless be in electrical communication. For example, the presence of a relatively thin film (e.g., up to about 100 nm) of a nucleation promoting material or a nucleation inhibiting material between the auxiliary electrode 3856 or 4056 and the second electrode 3850 or 4050 may still sufficiently allow a current to pass therethrough, thus allowing a sheet resistance of the second electrode 3850 or 4050 to be reduced.

FIG. 42 illustrates a structure of an AMOLED device 4102 according to yet another embodiment in which an interface between a nucleation inhibiting coating 4154 and an auxiliary electrode 4156 is formed on a slanted surface created by PDLs 4146. The device 4102 includes an organic layer 4148 deposited between a first electrode 4144 and a second electrode 4150, and the nucleation inhibiting coating 4154 is deposited over a portion of the second electrode 4150 which corresponds to an emissive region of the device 4102. The auxiliary electrode 4156 is deposited over portions of the second electrode 4150 that are exposed from the nucleation inhibiting coating 4154.

While not shown, the AMOLED device 4102 of FIG. 42 may further include a nucleation promoting coating disposed between the auxiliary electrode 4156 and the second electrode 4150. The nucleation promoting coating may also be disposed between the nucleation inhibiting coating 4154 and the second electrode 4150, particularly in cases where the nucleation promoting coating is deposited using an open mask or a mask-free deposition process.

FIG. 43 illustrates a portion of an AMOLED device 4300 according to yet another embodiment wherein the AMOLED device 4300 includes a plurality of light transmissive regions. As illustrated, the AMOLED device 4300 includes a plurality of pixels 4321 and an auxiliary electrode 4361 disposed between neighboring pixels 4321. Each pixel 4321 includes a subpixel region 4331, which further includes a plurality of subpixels 4333, 4335, 4337, and a light transmissive region 4351. For example, the subpixel 4333 may correspond to a red subpixel, the subpixel 4335 may correspond to a green subpixel, and the subpixel 4337 may correspond to a blue subpixel. As will be explained, the light transmissive region 4351 is substantially transparent to allow light to pass through the device 4300.

FIG. 44 illustrates a cross-sectional view of the device 4300 taken along line A-A as indicated in FIG. 43. Briefly, the device 4300 includes a base substrate 4310, a TFT 4308, an insulating layer 4342, and an anode 4344 formed on the insulating layer 4342 and in electrical communication with the TFT 4308. A first PDL 4346 a and a second PDL 4346 b are formed over the insulating layer 4342 and cover edges of the anode 4344. One or more organic layers 4348 are deposited to cover an exposed region of the anode 4344 and portions of the PDLs 4346 a, 4346 b. A cathode 4350 is then deposited over the one or more organic layers 4348. Next, a nucleation inhibiting coating 4354 is deposited to cover portions of the device 4300 corresponding to the light transmissive region 4351 and the subpixel region 4331. The entire device surface is then exposed to magnesium vapor flux, thus causing selective deposition of magnesium over an uncoated region of the cathode 4350. In this way, the auxiliary electrode 4361, which is in electrical contact with the underlying cathode 4350, is formed.

In the device 4300, the light transmissive region 4351 is substantially free of any materials which may substantially affect the transmission of light therethrough. In particular, the TFT 4308, the anode 4344, and the auxiliary electrode 4361 are all positioned within the subpixel region 4331 such that these components do not attenuate or impede light from being transmitted through the light transmissive region 4351. Such arrangement allows a viewer viewing the device 4300 from a typical viewing distance to see through the device 4300 when the pixels are off or are non-emitting, thus creating a transparent AMOLED display.

While not shown, the AMOLED device 4300 of FIG. 44 may further include a nucleation promoting coating disposed between the auxiliary electrode 4361 and the cathode 4350. The nucleation promoting coating may also be disposed between the nucleation inhibiting coating 4354 and the cathode 4350.

In other embodiments, various layers or coatings, including the organic layers 4348 and the cathode 4350, may cover a portion of the light transmissive region 4351 if such layers or coatings are substantially transparent. Alternatively, the PDLs 4346 a, 4346 b may not be provided in the light transmissive region 4351, if desired.

It will be appreciated that pixel and subpixel arrangements other than the arrangement illustrated in FIGS. 43 and 44 may also be used, and the auxiliary electrode 4361 may be provided in other regions of a pixel. For example, the auxiliary electrode 4361 may be provided in the region between the subpixel region 4331 and the light transmissive region 4351, and/or be provided between neighbouring subpixels, if desired.

In the foregoing embodiments, a nucleation inhibiting coating may, in addition to inhibiting nucleation and deposition of a conductive material (e.g., magnesium) thereon, act to enhance an out-coupling of light from a device. Specifically, the nucleation inhibiting coating may act as an index-matching coating and/or an anti-reflective coating.

A barrier coating (not shown) may be provided to encapsulate the devices illustrated in the foregoing embodiments depicting AMOLED display devices. As will be appreciated, such a barrier coating may inhibit various device layers, including organic layers and a cathode which may be prone to oxidation, from being exposed to moisture and ambient air. For example, the barrier coating may be a thin film encapsulation formed by printing, CVD, sputtering, ALD, any combinations of the foregoing, or by any other suitable methods. The barrier coating may also be provided by laminating a pre-formed barrier film onto the devices using an adhesive. For example, the barrier coating may be a multi-layer coating comprising organic materials, inorganic materials, or combination of both. The barrier coating may further comprise a getter material and/or a desiccant in some embodiments.

A sheet resistance specification for a common electrode of an AMOLED display device may vary according to a size of the display device (e.g., a panel size) and a tolerance for voltage variation. In general, the sheet resistance specification increases (e.g., a lower sheet resistance is specified) with larger panel sizes and lower tolerances for voltage variation across a panel.

The sheet resistance specification and an associated thickness of an auxiliary electrode to comply with the specification according to an embodiment were calculated for various panel sizes and plotted in FIG. 56. The sheet resistances and the auxiliary electrode thicknesses were calculated for voltage tolerances of 0.1 V and 0.2 V. Specifically, a voltage tolerance indicates a difference in voltage that would be supplied to pixels at an edge and those at a center of a panel to compensate for a combined IR drop of a transparent electrode and an auxiliary electrode as explained above. For the purpose of the calculation, an aperture ratio of 0.64 was assumed for all display panel sizes.

The specified thickness of the auxiliary electrode at example panel sizes are summarized in Table 2 below.

TABLE 2 Specified thickness of auxiliary electrode for various panel sizes Panel Size (inch) 9.7 12.9 15.4 27 65 Specified @0.1 V 132 239 335 1100 6500 Thickness (nm) @0.2 V  67 117 174  516 2800

As will be understood, various layers and portions of a backplane, including a thin-film transistor (TFT) (e.g., TFT 3804 shown in FIG. 39) may be fabricated using a variety of suitable materials and processes. For example, the TFT may be fabricated using organic or inorganic materials, which may be deposited and/or processed using techniques such as CVD, PECVD, laser annealing, and PVD (including sputtering). As would be understood, such layers may be patterned using photolithography, which uses a photomask to expose selective portions of a photoresist covering an underlying device layer to UV light. Depending on the type of photoresist used, exposed or unexposed portions of the photomask may then be washed off to reveal desired portion(s) of the underlying device layer. A patterned surface may then be etched, chemically or physically, to effectively remove an exposed portion of the device layer.

Furthermore, while a top-gate TFT has been illustrated and described in certain embodiments above, it will be appreciated that other TFT structures may also be used. For example, the TFT may be a bottom-gate TFT. The TFT may be an n-type TFT or a p-type TFT. Examples of TFT structures include those utilizing amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), and low-temperature polycrystalline silicon (LTPS).

Various layers and portions of a frontplane, including electrodes, one or more organic layers, a pixel definition layer, and a capping layer may be deposited using any suitable deposition processes, including thermal evaporation and/or printing. It will be appreciated that, for example, a shadow mask may be used as appropriate to produce desired patterns when depositing such materials, and that various etching and selective deposition processes may also be used to pattern various layers. Examples of such methods include, but are not limited to, photolithography, printing (including ink or vapor jet printing and reel-to-reel printing), OVPD, and LITI patterning.

While certain embodiments have been described above with reference to selectively depositing a conductive coating to form a cathode or an auxiliary electrode for a common cathode, it will be understood that similar materials and processes may be used to form an anode or an auxiliary electrode for an anode in other embodiments.

EXAMPLES

Aspects of some embodiments will now be illustrated and described with reference to the following examples, which are not intended to limit the scope of the present disclosure in any way.

As used in the examples herein, a reference to a layer thickness of a material refers to an amount of the material deposited on a target surface (or target region(s) of the surface in the case of selective deposition), which corresponds to an amount of the material to cover the target surface with an uniformly thick layer of the material having the referenced layer thickness. By way of example, depositing a layer thickness of 10 nm indicates that an amount of the material deposited on the surface corresponds to an amount of the material to form an uniformly thick layer of the material that is 10 nm thick. It will be appreciated that, for example, due to possible stacking or clustering of molecules or atoms, an actual thickness of the deposited material may be non-uniform. For example, depositing a layer thickness of 10 nm may yield some portions of the deposited material having an actual thickness greater than 10 nm, or other portions of the deposited material having an actual thickness less than 10 nm. A certain layer thickness of a material deposited on a surface can correspond to an average thickness of the deposited material across the surface.

Molecular structures of certain materials used in the illustrative examples are provided below.

Example 1

In order to characterize an interface between a nucleation inhibiting coating and an adjacent magnesium coating, a series of samples having varying layer thicknesses of the nucleation inhibiting coating and the magnesium coating were prepared and analyzed. Samples were prepared in a high vacuum deposition system with cryo-pumped processing chamber and turbo-molecular pumped load lock chamber using stainless steel shadow masks. Materials were thermally deposited from Knudsen cells (K-cells) using quartz crystal microbalances (QCMs) to monitor a deposition rate. A base pressure of the system was less than about 10⁻⁵ Pa, with a partial pressure of H₂O less than about 10⁻⁸ Torr during deposition. Magnesium was deposited at a source temperature of about 430-570° C. at a deposition rate of about 1-5 Å/sec. SEM micrographs were taken using a Hitachi S-5200.

The samples were prepared by first depositing about 30 nm of silver over a silicon substrate using thermal deposition. A nucleation inhibiting coating was then selectively deposited on a region of the silver surface using a shadow mask. In all of the samples, 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ) was used to form the nucleation inhibiting coating. Once the nucleation inhibiting coating was deposited, substantially pure magnesium (about 99.99% purity) was deposited using open mask deposition. More specifically, both an exposed silver surface and a nucleation inhibiting coating surface were subjected to an evaporated magnesium flux during the open mask deposition. The layer thicknesses of the nucleation inhibiting coating and associated deposition rates are summarized in Table 3 below. All depositions were conducted under vacuum (about 10⁻⁴ to about 10⁻⁶ Pa), and the layer thicknesses and deposition rates were monitored using a calibrated quartz crystal microbalance (QCM).

TABLE 3 TAZ and magnesium thicknesses and deposition rates TAZ Mg TAZ deposition Mg deposition thickness thickness rate rate Sample No. (nm) (nm) (Å/s) (Å/s) Sample 1 10 1160 0.2 2 Sample 2 100 500 0.7 2

The samples were analyzed using scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDX).

FIG. 45A is a SEM image of a top view of Sample 1. A first region 4501 of the image corresponds to a region over which magnesium has been deposited on top of the exposed silver surface, and a second region 4503 corresponds to a region covered by the nucleation inhibiting coating (TAZ). FIGS. 45B and 45C show a magnified top view of a portion of Sample 1 as shown in FIG. 45A. Based on the EDX elemental analysis, the presence of magnesium was not detected over a majority of the second region 4503. However, the formation of magnesium-containing islands or clusters 4505 was observed (see FIG. 45A), and the presence of magnesium in those islands 4503 was confirmed based on the EDX elemental analysis.

FIGS. 45D and 45E are SEM cross-sectional images of Sample 1, which shows an interface between the magnesium coating (the region 4501) and the nucleation inhibiting coating (region 4503). The underlying substrate 4510 can also be seen in these images.

FIGS. 45F and 45G are additional SEM cross-sectional images of Sample 1, taken at a different portion of the sample than FIGS. 45D and 45E.

As can be seen from FIGS. 45D-45G, the magnesium coating (the region 4501) includes a portion extending laterally over the nucleation inhibiting coating (the region 4503) in a partially overlapping region near the interface of the magnesium coating and the nucleation inhibiting coating. Specifically, the portion of the magnesium coating can be seen as forming an overhang which is not in direct contact with the surface of the nucleation inhibiting coating, thus creating a gap between the magnesium coating and the nucleation inhibiting coating at the interface.

FIG. 45H shows an EDX spectra taken from the first region 4501 and the second region 4503 of Sample 1. As can be seen from the plot of FIG. 45H, a peak corresponding to magnesium is clearly observed in the spectrum taken from the first region 4501, whereas no noticeable peak is detected in the spectrum taken from the second region 4503. The EDX measurements were taken at 5 keV over a sample area of about 2 pmt.

FIG. 46A is a SEM image of a top view of Sample 2. A first region 4601 of the image corresponds to a region over which magnesium has been deposited on top of the exposed silver surface, and a second region 4603 corresponds to a region covered by the nucleation inhibiting coating (TAZ). A magnified image of a portion of FIG. 46A is shown in FIG. 46B, and a further magnified image of a portion of FIG. 46B is shown in FIG. 46C. A cross-sectional profile of the sample is shown in the images of FIGS. 46D, 46E, and 46F, which also shows the substrate 4610. As can be seen in the images of FIGS. 46B-F, there is a relatively thin film or layer of magnesium 4607 deposited near the interface between the magnesium coating (the region 4601) and the TAZ coating (the region 4603). The presence of magnesium in the thin film 4607 was confirmed through EDX measurements. Also, the formation of magnesium-containing islands or clusters 4605 was observed (see FIG. 46A).

FIG. 46G shows an EDX spectra taken from the first region 4601 and the second region 4603 of Sample 2. As can be seen from the plot of FIG. 46G, a peak corresponding to magnesium is clearly observed in the spectrum taken from the first region 4601, whereas no noticeable peak is detected in the spectrum taken from the second region 4603. The EDX measurements were taken at 5 keV over a sample area of about 2 pmt.

FIG. 46H shows a linear EDX scan of the magnesium spectrum taken along a scan line of Sample 2. The EDX spectrum is overlaid on top of the corresponding SEM image to show the portion of the sample from which the EDX spectrum was obtained. As can be seen, the intensity of the magnesium spectrum begins to decrease at about 1.7 μm from the interface between the first region 4601 and the thin film 4607. This observation is consistent with the cross-sectional profile observed for the sample (e.g., FIG. 46D), which shows a thickness of the magnesium coating gradually decreasing or tapering near the interface.

Example 2

To measure properties of various materials for use as a nucleation inhibiting coating or a nucleation promoting coating, a series of experiments were conducted using a set of quartz crystal microbalances (QCMs).

As will be understood, a QCM can be used to monitor a rate of deposition in a thin film deposition process. Briefly, such monitoring is conducted by measuring a change in frequency of a quartz crystal resonator caused by addition or removal of a material on a surface of the resonator.

FIG. 47 is a schematic diagram illustrating an experimental set-up for measuring a deposition profile of magnesium on surfaces of QCMs. As illustrated, an evaporation chamber 4701 includes a first evaporation source 4710 and a second evaporation source 4712. A pair of QCMs 4731 and 4741 are positioned inside the chamber 4701 with a resonator surface of each of the QCMs 4731 and 4741 facing towards the sources 4710 and 4712. A sample shutter 4721 and a source shutter 4725 are disposed between the QCMs 4731 and 4741 and the evaporation sources 4710 and 4712. The sample shutter 4721 and the source shutter 4725 are moveable shutters adapted to control a flux of vapor incident on the QCMs 4731 and 4741 and the flux of vapor exiting from the sources 4710 and 4712, respectively.

In the illustrated example set up, the first QCM 4731, which will also be referred to herein as a “reference QCM”, serves as a baseline against which a deposition profile of magnesium on the second QCM 4741, which will also be referred to herein as a “sample QCM”, is compared. Optically polished quartz crystals obtained from LapTech Precision Inc. (part number: XL1252; frequency: 6.000 MHz; AT₁; center: 5.985 MHz; diameter: 13.97 mm±3 mm; optically polished) were used as the reference QCM and the sample QCM in each experiment.

Each experiment was conducted as follows. First, the reference QCM 4731 and the sample QCM 4741 were positioned inside the evaporation chamber 4701 as illustrated in FIG. 47. The chamber 4701 was then pumped down until the chamber pressure was below about 10⁻⁵ Pa. The sample shutter 4721 was then actuated such that the resonator surfaces of both the reference QCM 4731 and the sample QCM 4741 were masked. The first evaporation source 4710 was then initiated to start evaporation of a nucleation promoting or inhibiting material (also referred to as a “nucleation modifying material” herein). Once a stable evaporation rate was achieved, the sample shutter 4721 was moved such that the resonator surface of the sample QCM 4741 became exposed to the vapor flux while keeping the surface of the reference QCM 4731 unexposed, thus allowing the nucleation modifying material to be deposited on the surface of the sample QCM 4741. Upon depositing a desired layer thickness of the nucleation modifying material on the surface of the sample QCM 4741, the source shutter 4725 was actuated to block the vapor flux exiting the first source 4710, thus preventing further deposition. The first source 4710 was then shut off.

Next, the second evaporation source 4712 was initiated to start evaporation of magnesium. The shutter 4721 was used to cover the QCMs 4731 and 4741 until a stable deposition rate was reached. Once the stable deposition rate was reached, the shutter 4721 was actuated to uncover both the modified surface of the sample QCM 4741 and the surface of the reference QCM 4731, such that magnesium vapor was incident on the surfaces of both QCMs 4731 and 4741. The resonant frequencies of the QCMs 4731 and 4741 were monitored to determine the deposition profiles of magnesium on each of the QCMs 4731 and 4741.

Various nucleation modifying materials, including those that can be used to form a nucleation inhibiting coating, were deposited on the resonator surface of the sample QCM 4741 to form a nucleation modifying coating thereon. By repeating the above experimental procedure using the chamber configuration illustrated in FIG. 47 for each nucleation modifying material, the deposition rate of magnesium on various surfaces was analyzed. The following materials were used to form a nucleation modifying coating: 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ); aluminum (III) bis(2-methyl-8-quninolinato)-4-phenylphenolate (BAlq); 2-(4-(9,10-di(naphthalene-2-yl)anthracene-2-yl)phenyl)-1-phenyl-1H-benzo-[D]imidazole (LG201); 8-hydroxyquinoline lithium (Liq); and N(diphenyl-4-yl)9,9-dimethyl-N-(4(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluorene-2-amine (HT211).

FIG. 57 is a log-log plot showing a layer thickness of magnesium deposited on the reference QCM surface (reference layer thickness, or “deposited thickness” as labeled in FIG. 57) against a layer thickness of magnesium deposited on the sample QCM surface (sample layer thickness, or “average film thickness” as labeled in FIG. 57). In each case, the reference QCM surface was pre-coated with substantially pure silver prior to conducting the experiments.

Based on the plot of FIG. 57, the layer thicknesses of magnesium deposited on both QCM surfaces and thus the deposition rate of magnesium as a result of exposing the surfaces to the same magnesium vapor flux can be determined. In particular, by comparing the deposition rate of magnesium on the sample QCM surface to that on the reference QCM surface during the formation of a relatively thin layer of magnesium on the sample QCM surface (namely, during initial stages of deposition of up to 1 nm or 10 nm in layer thickness), the nucleation inhibiting properties of a coating present on the sample QCM surface may be determined. For ease of discussion, the layer thickness of magnesium deposited on the sample QCM surface will be referred to as the sample layer thickness, and the layer thickness of magnesium deposited on the reference QCM surface will be referred to as the reference layer thickness.

For certain experiments, the reference layer thickness corresponding to the sample layer thickness at 1 nm and 10 nm for various samples is summarized in Table 4 below. Specifically, the reference layer thickness provided in Table 4 corresponds to the layer thickness of magnesium deposited on the reference QCM surface in the same time period for a 1 nm or 10 nm layer thickness to be deposited on the sample QCM surface for each sample. Organic materials were deposited at a deposition rate of about 1 Å/sec at a vacuum pressure of about 10⁻⁵ Pa. Magnesium was deposited at a deposition rate of about 2 Å/sec at a source temperature of about 520-530° C. and a vacuum pressure of about 10⁻⁵ Pa.

TABLE 4 Summary of results of the sample layer thickness and corresponding reference layer thickness Nucleation Thickness of Thickness of Mg Modifying Mg on sample on reference QCM Material QCM surface (nm) surface (nm) TAZ 1 2158 BAlq 1 104 LG201 1 31 Liq 1 62 HT211 1 33

Based on the above, it can be seen that the reference layer thickness which was deposited when the sample layer thickness of 1 nm was reached varied substantially depending on the nucleation modifying material covering the sample QOM surface. A threshold sample layer thickness of 1 nm was selected in this example to determine the relative deposition rates during the initial stage of film formation on the sample QCM surface. It was observed that, since the reference QCM surface was pre-coated with silver, the deposition rate of magnesium on the reference QCM surface remained relatively constant.

A relatively thick coating of magnesium in excess of 2000 nm was deposited on the reference QCM before the sample layer thickness of 1 nm was reached for the sample QCM coated with TAZ. A reference layer thickness of 104 nm was deposited before the sample layer thickness of 1 nm was reached for the sample QCM coated with BAlq. However, a relatively thin coating of magnesium with a layer thickness less than 62 nm was deposited on the reference QCM before the threshold thickness was reached for the sample QCMs coated with LG201, Liq, or HT211.

As will be appreciated, a greater selectivity can generally be achieved during conductive coating deposition by using a nucleation modifying coating exhibiting a relatively high reference layer thickness, and thus a relatively low initial deposition rate and sticking probability. For example, a nucleation modifying coating exhibiting a high reference layer thickness may be an effective nucleation inhibiting coating, and may be used to cover region(s) of a target surface, such that when the target surface is exposed to magnesium vapor flux, magnesium selectively forms over uncovered region(s) of the target surface, with a surface of the nucleation inhibiting coating remaining substantially free of or substantially uncovered by magnesium. For example, a nucleation modifying coating exhibiting a reference layer thickness of at least or greater than about 80 nm at a threshold sample layer thickness of 1 nm may be used as a nucleation inhibiting coating. For example, a nucleation modifying coating exhibiting a reference layer thickness of at least or greater than about 100 nm, at least or greater than about 200 nm, at least or greater than about 500 nm, at least or greater than about 700 nm, at least or greater than about 1000 nm, at least or greater than about 1500 nm, at least or greater than about 1700 nm, or at least or greater than about 2000 nm at 1 nm threshold thickness may be used as a nucleation inhibiting coating. In other words, an initial deposition rate of magnesium on the reference surface may be at least or greater than about 80 times, at least or greater than about 100 times, at least or greater than about 200 times, at least or greater than about 500 times, at least or greater than about 700 times, at least or greater than about 1000 times, at least or greater than about 1500 times, at least or greater than about 1700 times, or at least or greater than about 2000 times an initial deposition rate of magnesium on a surface of the nucleation inhibiting coating.

FIG. 58 is a log-log plot of sticking probability of magnesium vapor on the sample QCM surface versus a layer thickness of magnesium deposited on the sample QCM surface.

The sticking probability was derived based on the following equation:

$S = \frac{N_{ads}}{N_{total}}$ wherein N_(ads) is a number of adsorbed monomers that are incorporated into a magnesium coating on the surface of the sample QCM, and N_(total) is a total number of impinging monomers on the surface, which was determined based on monitoring the deposition of magnesium on the reference QCM.

As can be seen from the plot of FIG. 58, the sticking probability generally increases as more magnesium is deposited on the surface. For the purpose of achieving selective deposition of a magnesium coating, a nucleation inhibiting coating exhibiting a relatively low initial sticking probability (e.g., a low sticking probability during an initial deposition stage) is desirably used. More specifically, an initial sticking probability of this example refers to the sticking probability measured upon depositing an amount of magnesium corresponding to forming a close-packed magnesium layer with an average thickness of 1 nm on a surface of a nucleation inhibiting coating. The sticking probability measured upon deposition of 1 nm layer thickness of magnesium on various nucleation inhibiting coating surfaces are summarized in Table 5 below.

TABLE 5 Summary of results of sticking probability Nucleation Sticking probability upon Inhibiting Material deposition of 1 nm of Mg TAZ <0.001 BAlq 0.013 LG201 0.042 Liq 0.045 HT211 0.064

Based on the experiments, coatings exhibiting an initial sticking probability of no greater than or less than about 0.03 (or 3%) with respect to magnesium vapor may act as a nucleation inhibiting coating. As would be understood, nucleation inhibiting coatings with lower initial sticking probability may be more desirable for some applications, such as for achieving deposition of a relatively thick magnesium coating. For example, coatings with an initial sticking probability of no greater than or less than about 0.02, no greater than or less than about 0.01, no greater than or less than about 0.08, no greater than or less than about 0.005, no greater than or less than about 0.003, no greater than or less than about 0.001, no greater than or less than about 0.0008, no greater than or less than about 0.0005, or no greater than or less than about 0.0001 may be used as a nucleation inhibiting coating. For example, such nucleation inhibiting coating may include those formed by depositing BAlq and/or TAZ.

Example 3

In order to characterize a correlation between a lateral growth of a magnesium coating near interfaces with adjacent coatings and a vertical growth of the magnesium coating, a series of samples with varying magnesium and TAZ layer thicknesses were prepared.

The samples were prepared by first depositing about 30 nm of silver over a silicon substrate using thermal deposition. A nucleation inhibiting coating was then selectively deposited on regions of the silver surface using a shadow mask. In all of the samples, 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ) was used to form the nucleation inhibiting coating. Once the nucleation inhibiting coating was deposited, substantially pure magnesium (about 99.99% purity) was deposited using open mask deposition such that both an exposed silver surface and a nucleation inhibiting coating surface were subjected to an evaporated magnesium flux during the open mask deposition. All depositions were conducted under vacuum (about 10⁻⁴ to about 10⁻⁶ Pa). Magnesium was deposited at a rate of about 2 Å/s.

FIG. 49 is a schematic diagram illustrating the samples that were prepared. As shown, portions 4901 and 4903 of the nucleation inhibiting coating were selectively deposited on regions of the silver surface, and the magnesium coating 4907 was deposited between the portions 4901 and 4903. For ease of discussion, the silicon substrate and the silver layer have been omitted from the diagram of FIG. 49. A lateral distance of the exposed silver surface located between the portions 4901 and 4903 of the nucleation inhibiting coating is shown as d, and a width of the magnesium coating 4907 is shown as d+Δd. In this way, a lateral growth distance of the magnesium coating 4907 can be determined by subtracting the lateral distance of the exposed silver surface from the width of the magnesium coating 4907. Both d and d+Δd were measured by conducting an analysis of top view SEM images of the samples. The layer thickness of magnesium, h, was monitored using a quartz crystal microbalance (QCM) during the deposition process.

The lateral growth distance (Δd) measured for the samples with varying magnesium layer thicknesses (h) and nucleation inhibiting layer thicknesses are summarized in Table 6 below. The measurement accuracy of Δd is about 0.5 μm.

TABLE 6 Lateral growth distance of Mg for various Mg and TAZ layer thicknesses h (μm) Δd (μm) (TAZ 10 nm) Δd (μm) (TAZ 100 nm) 0.25 <0.5 <0.5 0.75 2.5 <0.5 1.5 3.5 —

As can be observed from the above results, no detectable amount of lateral growth was observed in the samples prepared with a relatively thick TAZ coating. Specifically, no lateral growth was detected for the samples prepared with 100 nm of TAZ nucleation inhibiting coating and 0.25 μm and 0.75 μm of magnesium coating.

For the samples prepared with a relatively thin (10 nm layer thickness) TAZ coating, no lateral growth was detected for the sample with 0.25 μm thick magnesium coating. However, for the samples prepared with thicker magnesium coatings, lateral growth of magnesium was observed. Specifically, the sample prepared with 10 nm thick TAZ nucleation inhibiting coating and 0.75 μm thick magnesium coating exhibited lateral magnesium growth of about 2.5 μm, and the sample prepared with 10 nm thick TAZ nucleation inhibiting coating and 1.5 μm thick magnesium coating exhibited lateral growth of about 3.5 μm.

Example 4

A sample was prepared using another nucleation inhibiting coating including BAlq.

Specifically, the sample was fabricated according to the following structure: silicon base substrate/LG201 (40 nm)/Mg:Ag (20 nm)/BAlq (500 nm)/Mg (300 nm). Specifically, about 40 nm of 2-(4-(9,10-di(naphthalene-2-yl)anthracene-2-yl)phenyl)-1-phenyl-1H-benzo-[D]imidazole (LG201) was deposited on a silicon substrate, followed by about 20 nm of Mg:Ag (including Mg:Ag in about 1:9 proportion by volume). The nucleation inhibiting coating in the form of about 500 nm of aluminum (III) bis(2-methyl-8-quninolinato)-4-phenylphenolate (BAlq) was then selectively deposited over regions of the Mg:Ag surface. Once the nucleation inhibiting coating was deposited, substantially pure magnesium (about 99.99% purity) was deposited using open mask deposition such that both an exposed Mg:Ag surface and a nucleation inhibiting coating surface were subjected to an evaporated magnesium flux during the open mask deposition. All depositions were conducted under vacuum (about 10⁻⁴ to about 10⁻⁶ Pa). The magnesium coating was deposited at rate of about 3.5 Å/s.

FIG. 50A is a SEM image of a top view of the sample prepared using the BAlq nucleation inhibiting coating. A first region 5003 corresponds to a region where the BAlq coating was present and thus no significant amount of magnesium was deposited, and a second region 5001 corresponds to a region where magnesium was deposited. FIGS. 50C and 50D show a magnified view of regions 5007 and 5005, respectively. FIG. 50B shows a magnified view of an interface between the first region 5003 and the second region 5001.

As can be seen in FIG. 50B, there were a number of islands 5011 formed near the interface. Specifically, the islands 5011 are generally disconnected magnesium-containing clusters which form on the surface of the nucleation inhibiting coating. For example, it is postulated that islands may include magnesium and/or magnesium oxide.

FIG. 50C shows the magnified view of the region 5007 in FIG. 50A, which is a region representative of a “bulk” of the magnesium coating formed by the process. FIG. 50D shows the magnified view of the region 5005, which is near the interface between the first region 5003 and the second region 5001. As can be seen, a morphology of the magnesium coating near the interface differs from that in the bulk of the coating.

FIG. 50E further shows a cross-sectional SEM image of the sample, where the islands 5011 are shown on the surface of the nucleation inhibiting coating.

Example 5 Comparative Example A

A comparative sample was prepared to characterize a structure formed using a material exhibiting relatively poor nucleation inhibiting properties (e.g., a nucleation inhibiting coating exhibits a relatively high initial sticking coefficient for magnesium vapor).

The comparative sample was fabricated according to the following structure: silicon base substrate/LG201 (40 nm)/Mg:Ag(20 nm)/HT211 (500 nm)/Mg (300 nm). Specifically, about 40 nm of 2-(4-(9,10-di(naphthalene-2-yl)anthracene-2-yl)phenyl)-1-phenyl-1H-benzo-[D]imidazole (LG201) was deposited on a silicon substrate, followed by about 20 nm of Mg:Ag (about 1:9 by volume). The nucleation inhibiting coating in the form of about 500 nm of N(diphenyl-4-yl)9,9-dimethyl-N-(4(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluorene-2-amine (HT211) was then selectively deposited over regions of the Mg:Ag surface. Once the nucleation inhibiting coating was deposited, substantially pure magnesium (about 99.99% purity) was deposited using open mask deposition such that both an exposed Mg:Ag surface and a nucleation inhibiting coating surface were subjected to an evaporated magnesium flux during the open mask deposition. All depositions were conducted under vacuum (about 10⁻⁴ to about 10⁻⁶ Pa). The magnesium coating was deposited at rate of about 3.5 Å/s.

FIG. 51A shows a top view SEM image of the comparative sample, where a first region 5103 corresponds to a region over which the nucleation inhibiting coating in the form of HT211 was deposited, and a second region 5101 corresponds to a region where the magnesium coating was formed. As can be seen, a significant amount of magnesium in the first region 5103 can be clearly observed.

FIG. 51B shows a cross-sectional SEM image of the comparative sample. An approximate interface between the first region 5103 and the second region 5101 is indicated using a dotted line.

Example 6 Comparative Example B

Another comparative sample was prepared to determine a profile of a magnesium coating deposited on a surface using a shadow mask technique.

The comparative sample was fabricated by depositing about 30 nm layer thickness of silver on top of a silicon wafer, followed by shadow mask deposition of about 800 nm layer thickness of magnesium. Specifically, the shadow mask deposition was configured to allow certain regions of the silver surface to be exposed to a magnesium flux through a shadow mask aperture while masking other regions of the silver surface. Magnesium was deposited at a rate of about 2 Å/s.

FIG. 52A is a top view of a SEM image of the comparative sample. An approximate interface is shown using a dotted line in FIG. 52A. A first region 5203 corresponds to the masked region, and a second region 5201 corresponds to the exposed region over which a magnesium coating was deposited.

FIG. 52B is a cross-sectional SEM image of the comparative sample. As can be seen in FIG. 52B, the magnesium coating deposited over the second region 5201 includes a relatively long (about 6 μm) tapering or tail portion 5214 where a thickness of the portion 5214 gradually tapers.

Example 7 Comparative Example C

To characterize an effect of deposition rate on a nucleation inhibiting property of a nucleation inhibiting coating including HT211, a series of comparative samples with varying layer thicknesses of HT211 were fabricated.

Specifically, the samples were fabricated by depositing about 10 nm layer thickness of HT211 over an entire surface of a glass substrate, followed by open mask deposition of magnesium. Various evaporation rates were used to deposit a magnesium coating; however in preparing each sample, a deposition time was adjusted accordingly to obtain a reference layer thickness of magnesium of either about 100 nm or about 1000 nm.

As used in this example, a reference layer thickness refers to a layer thickness of magnesium that is deposited on a reference surface exhibiting a high initial sticking coefficient (e.g., a surface with an initial sticking coefficient of about or close to 1.0). For example, the reference surface may be a surface of a QCM positioned inside a deposition chamber for the purpose of monitoring a deposition rate and the reference layer thickness. In other words, the reference layer thickness does not indicate an actual thickness of magnesium deposited on a target surface (e.g., a surface of the nucleation inhibiting coating), but rather refers to the layer thickness of magnesium that is deposited on the reference surface.

FIG. 53 shows a plot of transmittance versus wavelength for various samples fabricated using various deposition rates and associated reference layer thicknesses. Based on the transmittance data, it can be seen that a sample with a relatively low magnesium reference layer thickness of about 100 nm, which was deposited at a low deposition rate of about 0.2 Å/s, exhibited the highest transmittance. However, when a sample with substantially identical reference layer thickness was deposited at a higher deposition rate of about 2 Å/s, the transmittance was lower across an entire measured spectrum. The lowest transmittance was detected for a sample with a relatively high magnesium reference layer thickness of about 1000 nm deposited using a relatively high rate of about 2 Å/s.

It is postulated that the reduced transmittance observed in the blue region (about 400-475 nm) of the spectrum for all three samples may be attributed to absorption by magnesium oxide, which may be present in the samples due to oxidation of the deposited magnesium.

Example 8

In order to characterize an effect of using various materials to form a nucleation inhibiting coating, a series of samples were prepared using different materials to form the nucleation inhibiting coating.

The samples were fabricated by depositing about 10 nm layer thickness of the nucleation inhibiting coating on top of a glass substrate surface. The samples were then subjected to open mask deposition of magnesium. For each of the samples, magnesium was deposited at a rate of about 2 Å/s until a reference layer thickness of about 1000 nm was reached.

FIG. 54 is a plot of transmittance versus wavelength for the samples fabricated with various materials. As can be seen, the sample fabricated with TAZ exhibited the highest transmittance, followed by BAlq. Both samples fabricated with HT211 and Liq were found to exhibit substantially lower transmittance compared to those prepared with TAZ and BAlq, due to a greater amount of magnesium being deposited on surfaces of HT211 and Liq.

Example 9

A series of samples were prepared to assess an effect of providing an auxiliary electrode according to an example embodiment.

A first reference sample was prepared by depositing a layer of Mg:Ag on a substrate surface to replicate a typical common cathode used in a top-emission AMOLED display device.

A second reference sample was prepared by selectively depositing an auxiliary electrode in the form of a repeating grid on top of a non-conducting substrate surface. A pattern of the auxiliary electrode is shown in FIG. 55. Specifically, the auxiliary electrode 5501 includes a plurality of apertures 5505 formed therein, such that if the auxiliary electrode 5501 is fabricated on an AMOLED device, each aperture 5505 would substantially correspond to an emissive region (e.g., a pixel or subpixel) of the device with the auxiliary electrode 5501 being deposited on a non-emissive region (e.g., an inter-pixel or inter-subpixel region). An average width or size of each aperture 5505 was about 70 μm, and a width of each strip or segment of the auxiliary electrode 5501 was about 15-18 μm. The auxiliary electrode 5501 was formed using substantially pure (about 99.99% purity) magnesium.

An evaluation sample was prepared by depositing an auxiliary electrode (under the conditions used for the second reference sample) on top of the Mg:Ag layer of the first reference sample. Specifically, a nucleation inhibiting coating was selectively deposited on top of the Mg:Ag layer using a shadow mask, and a resulting patterned surface was then exposed to magnesium vapor to selectively deposit the magnesium auxiliary electrode to result in a similar pattern as shown in FIG. 55.

Sheet resistances of the samples were measured, and results of the measurements are summarized in Table 7 below.

TABLE 7 Sheet resistance measurements First Reference Second Reference Evaluation Sample Sample Sample Sheet Resistance 22.3 0.13 0.1 (ohm/sq)

As shown in the table above, the first reference sample (Mg:Ag layer) was found to exhibit a relatively high sheet resistance of about 22.3 Ω/sq. The second reference sample and the evaluation sample were found to have substantially lower sheet resistances of about 0.13 Ω/sq and about 0.1 Ω/sq, respectively. Accordingly, it was confirmed that, by providing an auxiliary electrode according to the example embodiment in electrical connection with a thin film conductor (e.g., a common cathode), the sheet resistance of the thin film conductor may be substantially reduced.

As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

In the description of some embodiments, a component provided “on” or “over” another component, or “covering” or which “covers” another component, can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.

Although the present disclosure has been described with reference to certain specific embodiments, various modifications thereof will be apparent to those skilled in the art. Any examples provided herein are included solely for the purpose of illustrating certain aspects of the disclosure and are not intended to limit the disclosure in any way. Any drawings provided herein are solely for the purpose of illustrating certain aspects of the disclosure and may not be drawn to scale and do not limit the disclosure in any way. The scope of the claims appended hereto should not be limited by the specific embodiments set forth in the above description, but should be given their full scope consistent with the present disclosure as a whole. The disclosures of all documents recited herein are incorporated herein by reference in their entirety. 

The invention claimed is:
 1. An opto-electronic device comprising: a substrate; a nucleation inhibiting coating covering a first region of the substrate; and a conductive coating including a first portion and a second portion, the first portion of the conductive coating covering a second region of the substrate, and the second portion of the conductive coating partially overlapping the nucleation inhibiting coating, wherein the second portion of the conductive coating is spaced from the nucleation inhibiting coating by a gap, and wherein the conductive coating further includes a third portion in contact with the nucleation inhibiting coating, and the third portion of the conductive coating includes disconnected clusters on a surface of the nucleation inhibiting coating.
 2. The opto-electronic device of claim 1, wherein the second portion of the conductive coating extends over an overlapping portion of the nucleation inhibiting coating, and is spaced from the overlapping portion of the nucleation inhibiting coating by the gap.
 3. The opto-electronic device of claim 2, wherein another portion of the nucleation inhibiting coating is exposed from the conductive coating.
 4. The opto-electronic device of claim 1, wherein and a thickness of the third portion of the conductive coating is no greater than 5% of a thickness of the first portion of the conductive coating.
 5. The opto-electronic device of claim 4, wherein the second portion of the conductive coating extends over the third portion of the conductive coating, and is spaced from the third portion of the conductive coating.
 6. The opto-electronic device of claim 1, wherein the conductive coating further includes an intermediate portion disposed between the first portion of the conductive coating and the second portion of the conductive coating, and the intermediate portion of the conductive coating is in contact with the nucleation inhibiting coating.
 7. The opto-electronic device of claim 1, wherein the nucleation inhibiting coating includes a polymer.
 8. The opto-electronic device of claim 7, wherein the polymer is selected from the group consisting of: fluoropolymer, polyvinylbiphenyl, and polyvinylcarbazole.
 9. The opto-electronic device of claim 7, wherein the polymer is a fluoropolymer.
 10. The opto-electronic device of claim 9, wherein the fluoropolymer is selected from a group consisting of: perfluorinated polymer and polytetrafluoroethylene.
 11. The opto-electronic device of claim 1, wherein the nucleation inhibiting coating includes a polycyclic aromatic compound.
 12. The opto-electronic device of claim 1, wherein the nucleation inhibiting coating includes an organic compound including a core moiety and a terminal moiety bonded to the core moiety, and the terminal moiety includes a biphenylyl moiety, a phenyl moiety, a fluorene moiety, or a phenylene moiety.
 13. The opto-electronic device of claim 12, wherein the core moiety includes a cyclic hydrocarbon moiety.
 14. The opto-electronic device of claim 1, wherein the conductive coating includes magnesium.
 15. The opto-electronic device of claim 1, wherein the nucleation inhibiting coating is characterized as having an initial sticking probability for a material of the conductive coating of no greater than 0.02.
 16. The opto-electronic device of claim 1, wherein the substrate includes a backplane and a frontplane disposed on the backplane.
 17. The opto-electronic device of claim 16, wherein the backplane includes a transistor, and the frontplane includes an electrode electrically connected to the transistor, and at least one organic layer disposed on the electrode.
 18. The opto-electronic device of claim 17, wherein the electrode is a first electrode, and the frontplane further includes a second electrode disposed on the organic layer.
 19. The opto-electronic device of claim 18, wherein the conductive coating forms the second electrode.
 20. The opto-electronic device of claim 1, wherein the opto-electronic device is an organic light emitting diode (OLED) device, and the OLED device includes a light transmissive portion configured to transmit light therethrough.
 21. The opto-electronic device of claim 20, wherein the nucleation inhibiting coating is deposited in the light transmissive portion.
 22. An opto-electronic device comprising: a substrate; a nucleation inhibiting coating covering a first region of the substrate; and a conductive coating covering a laterally adjacent, second region of the substrate, wherein the conductive coating includes an electrically conductive material, and the nucleation inhibiting coating is characterized as having an initial sticking probability for the electrically conductive material of no greater than 0.02, and wherein the conductive coating further includes a portion in contact with the nucleation inhibiting coating, and the portion of the conductive coating includes disconnected clusters on a surface of the nucleation inhibiting coating.
 23. The opto-electronic device of claim 22, wherein the nucleation inhibiting coating includes a polymer.
 24. The opto-electronic device of claim 23, wherein the polymer is selected from the group consisting of: fluoropolymer, polyvinylbiphenyl, and polyvinylcarbazole.
 25. The opto-electronic device of claim 23, wherein the polymer is a fluoropolymer.
 26. The opto-electronic device of claim 25, wherein the fluoropolymer is selected from a group consisting of: perfluorinated polymer and polytetrafluoroethylene.
 27. The opto-electronic device of claim 22, wherein the electrically conductive material includes magnesium.
 28. The opto-electronic device of claim 22, wherein the opto-electronic device is an organic light emitting diode (OLED) device, and the OLED device includes a light transmissive portion configured to transmit light therethrough.
 29. The opto-electronic device of claim 28, wherein the nucleation inhibiting coating is provided in the light transmissive portion.
 30. The opto-electronic device of claim 28, wherein the conductive coating is an electrode of the OLED device. 